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74LVQ240SCX_NL PDF预览

74LVQ240SCX_NL

更新时间: 2024-11-17 13:04:59
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 驱动器
页数 文件大小 规格书
6页 92K
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74LVQ240SCX_NL 数据手册

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May 1998  
74LVQ240  
Low Voltage Octal Buffer/Line Driver with 3-STATE  
Outputs  
General Description  
Features  
n Ideal for low power/low noise 3.3V applications  
n Implements patented EMI reduction circuitry  
The LVQ240 is an inverting octal buffer and line driver de-  
signed to be employed as a memory address driver, clock  
driver and bus oriented transmitter or receiver which pro-  
vides improved PC board density.  
n Available in SOIC JEDEC, SOIC EIAJ, and QSOP  
packages  
n Guaranteed simultaneous switching noise level and  
dynamic threshold performance  
n Improved latch-up immunity  
n Guaranteed incident wave switching into 75  
n 4 kV minimum ESD immunity  
Ordering Code:  
Order Number  
74LVQ240SC  
74LVQ240SJ  
Package Number  
M20B  
Package Description  
20-Lead (0.300" Wide) Molded Small Outline Package, SOIC, JEDEC  
20-Lead Molded Shrink Small Outline Package, SOIC, EIAJ  
20-Lead (0.150" Wide) Molded Shrink Small Outline Package, SSOP, JEDEC  
M20D  
74LVQ240QSC  
MQA20  
Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.  
Logic Symbol  
Connection Diagram  
IEEE/IEC  
Pin Assignment,  
SOIC and QSOP  
DS011611-1  
Pin Descriptions  
Pin Names  
Description  
OE1, OE2  
I0–I7  
3-STATE Output Enable Inputs  
DS011611-2  
Inputs  
Truth Tables  
O0–O7  
Outputs  
Inputs  
Outputs  
(Pins 12, 14, 16, 18)  
OE1  
L
In  
L
H
X
H
L
L
H
Z
Inputs  
Outputs  
OE2  
L
In  
L
(Pins 3, 5, 7, 9)  
H
L
L
H
X
H
Z
=
=
=
=
H
X
HIGH Voltage Level  
Immaterial  
L
Z
LOW Voltage Level  
High Impedance  
© 1998 Fairchild Semiconductor Corporation  
DS011611  
www.fairchildsemi.com  

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