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74LVQ241QSCX PDF预览

74LVQ241QSCX

更新时间: 2024-11-19 23:24:27
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 总线驱动器总线收发器逻辑集成电路光电二极管输出元件
页数 文件大小 规格书
6页 65K
描述
Dual 4-Bit Non-Inverting Buffer/Driver

74LVQ241QSCX 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:SSOP包装说明:SSOP, SSOP20,.25
针数:20Reach Compliance Code:unknown
风险等级:5.47其他特性:OUTPUT ENABLE ACTIVE HIGH FOR ONE FUNCTION
控制类型:ENABLE LOW/HIGH系列:LVQ
JESD-30 代码:R-PDSO-G20JESD-609代码:e3
长度:8.65 mm负载电容(CL):50 pF
逻辑集成电路类型:BUS DRIVER最大I(ol):0.012 A
湿度敏感等级:1位数:4
功能数量:2端口数量:2
端子数量:20最高工作温度:85 °C
最低工作温度:-40 °C输出特性:3-STATE
输出极性:TRUE封装主体材料:PLASTIC/EPOXY
封装代码:SSOP封装等效代码:SSOP20,.25
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, SHRINK PITCH
峰值回流温度(摄氏度):260电源:3.3 V
Prop。Delay @ Nom-Sup:9.5 ns传播延迟(tpd):14 ns
认证状态:Not Qualified座面最大高度:1.75 mm
子类别:Bus Driver/Transceivers最大供电电压 (Vsup):3.6 V
最小供电电压 (Vsup):2 V标称供电电压 (Vsup):2.7 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:Matte Tin (Sn)
端子形式:GULL WING端子节距:0.635 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:3.9116 mmBase Number Matches:1

74LVQ241QSCX 数据手册

 浏览型号74LVQ241QSCX的Datasheet PDF文件第2页浏览型号74LVQ241QSCX的Datasheet PDF文件第3页浏览型号74LVQ241QSCX的Datasheet PDF文件第4页浏览型号74LVQ241QSCX的Datasheet PDF文件第5页浏览型号74LVQ241QSCX的Datasheet PDF文件第6页 
February 1992  
Revised June 2001  
74LVQ241  
Low Voltage Octal Buffer/Line Driver  
with 3-STATE Outputs  
General Description  
Features  
Ideal for low power/low noise 3.3V applications  
The LVQ241 is an octal buffer and line driver designed to  
be employed as a memory address driver, clock driver and  
bus oriented transmitter or receiver which provides  
improved PC board density.  
Implements patented EMI reduction circuitry  
Available in SOIC JEDEC, SOIC EIAJ and QSOP pack-  
ages  
Guaranteed simultaneous switching noise level and  
dynamic threshold performance  
Improved latch-up immunity  
Guaranteed incident wave switching into 75  
4 kV minimum ESD immunity  
Ordering Code:  
Order Number  
74LVQ241SC  
74LVQ241SJ  
Package Number  
M20B  
Package Description  
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide  
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide  
20-Lead Quarter Size Outline Package (QSOP), JEDEC MO-137, 0.150" Wide  
M20D  
74LVQ241QSC  
MQA20  
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.  
Logic Diagram  
Connection Diagram  
IEEE/IEC  
Truth Tables  
Inputs  
OE1  
Outputs  
In  
(Pins 12, 14, 16, 18)  
Pin Descriptions  
L
L
L
H
X
L
H
Z
Pin Names  
Description  
H
OE1, OE2  
I0I7  
3-STATE Output Enable Inputs  
Inputs  
OE2  
Outputs  
Inputs  
In  
(Pins 3, 5, 7, 9)  
O0O7  
Outputs  
L
H
H
X
H
L
Z
H
L
H = HIGH Voltage Level X = Immaterial  
L = LOW Voltage Level Z = High Impedance  
© 2001 Fairchild Semiconductor Corporation  
DS011355  
www.fairchildsemi.com  

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