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74LVQ241SJ PDF预览

74LVQ241SJ

更新时间: 2024-11-19 22:53:19
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 驱动器
页数 文件大小 规格书
6页 65K
描述
Low Voltage Octal Buffer/Line Driver with 3-STATE Outputs

74LVQ241SJ 数据手册

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February 1992  
Revised June 2001  
74LVQ241  
Low Voltage Octal Buffer/Line Driver  
with 3-STATE Outputs  
General Description  
Features  
Ideal for low power/low noise 3.3V applications  
The LVQ241 is an octal buffer and line driver designed to  
be employed as a memory address driver, clock driver and  
bus oriented transmitter or receiver which provides  
improved PC board density.  
Implements patented EMI reduction circuitry  
Available in SOIC JEDEC, SOIC EIAJ and QSOP pack-  
ages  
Guaranteed simultaneous switching noise level and  
dynamic threshold performance  
Improved latch-up immunity  
Guaranteed incident wave switching into 75  
4 kV minimum ESD immunity  
Ordering Code:  
Order Number  
74LVQ241SC  
74LVQ241SJ  
Package Number  
M20B  
Package Description  
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide  
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide  
20-Lead Quarter Size Outline Package (QSOP), JEDEC MO-137, 0.150" Wide  
M20D  
74LVQ241QSC  
MQA20  
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.  
Logic Diagram  
Connection Diagram  
IEEE/IEC  
Truth Tables  
Inputs  
OE1  
Outputs  
In  
(Pins 12, 14, 16, 18)  
Pin Descriptions  
L
L
L
H
X
L
H
Z
Pin Names  
Description  
H
OE1, OE2  
I0I7  
3-STATE Output Enable Inputs  
Inputs  
OE2  
Outputs  
Inputs  
In  
(Pins 3, 5, 7, 9)  
O0O7  
Outputs  
L
H
H
X
H
L
Z
H
L
H = HIGH Voltage Level X = Immaterial  
L = LOW Voltage Level Z = High Impedance  
© 2001 Fairchild Semiconductor Corporation  
DS011355  
www.fairchildsemi.com  

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