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74LVQ244MSA PDF预览

74LVQ244MSA

更新时间: 2024-11-17 13:04:59
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 驱动器
页数 文件大小 规格书
6页 65K
描述
Bus Driver, LVQ Series, 2-Func, 4-Bit, True Output, PDSO20

74LVQ244MSA 技术参数

生命周期:Obsolete包装说明:SSOP,
Reach Compliance Code:unknown风险等级:5.68
Is Samacsys:N系列:LVQ
JESD-30 代码:R-PDSO-G20长度:7.2 mm
逻辑集成电路类型:BUS DRIVER位数:4
功能数量:2端口数量:2
端子数量:20最高工作温度:85 °C
最低工作温度:-40 °C输出特性:3-STATE
输出极性:TRUE封装主体材料:PLASTIC/EPOXY
封装代码:SSOP封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, SHRINK PITCH传播延迟(tpd):14 ns
认证状态:Not Qualified座面最大高度:2.05 mm
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):2 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
温度等级:INDUSTRIAL端子形式:GULL WING
端子节距:0.65 mm端子位置:DUAL
宽度:5.3 mmBase Number Matches:1

74LVQ244MSA 数据手册

 浏览型号74LVQ244MSA的Datasheet PDF文件第2页浏览型号74LVQ244MSA的Datasheet PDF文件第3页浏览型号74LVQ244MSA的Datasheet PDF文件第4页浏览型号74LVQ244MSA的Datasheet PDF文件第5页浏览型号74LVQ244MSA的Datasheet PDF文件第6页 
February 1992  
Revised June 2001  
74LVQ244  
Low Voltage Octal Buffer/Line Driver  
with 3-STATE Outputs  
General Description  
Features  
Ideal for low power/low noise 3.3V applications  
The LVQ244 is an octal buffer and line driver designed to  
be employed as a memory address driver, clock driver and  
bus oriented transmitter or receiver which provides  
improved PC board density.  
Implements patented EMI reduction circuitry  
Available in SOIC JEDEC, SOIC EIAJ and QSOP pack-  
ages  
Guaranteed simultaneous switching noise level and  
dynamic threshold performance  
Improved latch-up immunity  
Guaranteed incident wave switching into 75  
4 kV minimum ESD immunity  
Ordering Code:  
Order Number  
74LVQ244SC  
74LVQ244SJ  
Package Number  
M20B  
Package Description  
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide  
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide  
20-Lead Quarter Size Outline Package (QSOP), JEDEC MO-137, 0.150" Wide  
M20D  
74LVQ244QSC  
MQA20  
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.  
Logic Symbol  
Connection Diagram  
IEEE/IEC  
Truth Tables  
Inputs  
Outputs  
OE1  
In  
(Pins 12, 14, 16, 18)  
L
L
L
H
X
L
H
Z
Pin Descriptions  
Pin Names  
Description  
H
OE1, OE2  
I0I7  
3-STATE Output Enable Inputs  
Inputs  
Outputs  
Inputs  
OE2  
In  
(Pins 3, 5, 7, 9)  
O0O7  
Outputs  
L
L
L
H
X
L
H
Z
H
H = HIGH Voltage Level L = LOW Voltage Level  
X = Immaterial Z = High Impedance  
© 2001 Fairchild Semiconductor Corporation  
DS011356  
www.fairchildsemi.com  

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