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74LVQ240SJ PDF预览

74LVQ240SJ

更新时间: 2024-11-19 04:47:51
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 总线驱动器总线收发器逻辑集成电路光电二极管
页数 文件大小 规格书
12页 254K
描述
Low Voltage Octal Buffer/Line Driver with 3-STATE Outputs

74LVQ240SJ 数据手册

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74LVQ240  
LOW VOLTAGE OCTAL BUS BUFFER  
WITH 3 STATE OUTPUTS (INVERTED)  
HIGH SPEED:  
= 6 ns (TYP.) at V = 3.3 V  
t
PD  
CC  
COMPATIBLE WITH TTL OUTPUTS  
LOW POWER DISSIPATION:  
I
= 4 µA (MAX.) at T =25°C  
CC  
A
LOW NOISE:  
= 0.4V (TYP.) at V = 3.3V  
75TRANSMISSION LINE OUTPUT DRIVE  
CAPABILITY  
SOP  
TSSOP  
V
OLP  
CC  
Table 1: Order Codes  
PACKAGE  
SYMMETRICAL OUTPUT IMPEDANCE:  
|I | = I = 12mA (MIN) at V = 3.0 V  
OH  
OL  
CC  
T & R  
PCI BUS LEVELS GUARANTEED AT 24 mA  
BALANCED PROPAGATION DELAYS:  
SOP  
74LVQ240MTR  
74LVQ240TTR  
TSSOP  
t
t
PLH  
PHL  
OPERATING VOLTAGE RANGE:  
(OPR) = 2V to 3.6V (1.2V Data Retention)  
PIN AND FUNCTION COMPATIBLE WITH  
74 SERIES 240  
V
technology. It is ideal for low power and low noise  
3.3V applications.  
G output control governs four BUS BUFFERs.  
This device is designed to be used with 3 state  
memory address drivers, etc.  
CC  
IMPROVED LATCH-UP IMMUNITY  
All inputs and outputs are equipped with  
protection circuits against static discharge, giving  
them 2KV ESD immunity and transient excess  
voltage.  
DESCRIPTION  
The 74LVQ240 is a low voltage CMOS OCTAL  
BUS BUFFER fabricated with sub-micron silicon  
2
gate and double-layer metal wiring C MOS  
Figure 1: Pin Connection And IEC Logic Symbols  
Rev. 7  
1/12  
July 2004  

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