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74LVQ240SJX PDF预览

74LVQ240SJX

更新时间: 2024-01-01 10:09:07
品牌 Logo 应用领域
其他 - ETC 驱动器逻辑集成电路光电二极管输出元件
页数 文件大小 规格书
6页 65K
描述
Dual 4-Bit Inverting Buffer/Driver

74LVQ240SJX 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:TSSOP包装说明:TSSOP-20
针数:20Reach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:5.68
Is Samacsys:N控制类型:ENABLE LOW
系列:LVQJESD-30 代码:R-PDSO-G20
JESD-609代码:e4长度:6.5 mm
负载电容(CL):50 pF逻辑集成电路类型:BUS DRIVER
最大I(ol):0.024 A位数:4
功能数量:2端口数量:2
端子数量:20最高工作温度:125 °C
最低工作温度:-55 °C输出特性:3-STATE
输出极性:INVERTED封装主体材料:PLASTIC/EPOXY
封装代码:TSSOP封装等效代码:TSSOP20,.25
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
包装方法:TAPE AND REEL峰值回流温度(摄氏度):NOT SPECIFIED
电源:3.3 VProp。Delay @ Nom-Sup:11 ns
传播延迟(tpd):14 ns认证状态:Not Qualified
座面最大高度:1.2 mm子类别:Bus Driver/Transceivers
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):2 V
标称供电电压 (Vsup):2.7 V表面贴装:YES
技术:CMOS温度等级:MILITARY
端子面层:NICKEL PALLADIUM GOLD端子形式:GULL WING
端子节距:0.65 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:4.4 mm
Base Number Matches:1

74LVQ240SJX 数据手册

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June 1993  
Revised June 2001  
74LVQ240  
Low Voltage Octal Buffer/Line Driver  
with 3-STATE Outputs  
General Description  
Features  
Ideal for low power/low noise 3.3V applications  
The LVQ240 is an inverting octal buffer and line driver  
designed to be employed as a memory address driver,  
clock driver and bus oriented transmitter or receiver which  
provides improved PC board density.  
Implements patented EMI reduction circuitry  
Available in SOIC JEDEC, SOIC EIAJ, and QSOP pack-  
ages  
Guaranteed simultaneous switching noise level and  
dynamic threshold performance  
Improved latch-up immunity  
Guaranteed incident wave switching into 75  
4 kV minimum ESD immunity  
Ordering Code:  
Order Number Package Number  
Package Description  
74LVQ240SC  
74LVQ240SJ  
74LVQ240QSC  
M20B  
M20D  
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide  
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide  
MQA20  
20-Lead Quarter Size Outline Package (QSOP), JEDEC MO-137, 0.150" Wide  
Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.  
Logic Symbol  
Pin Descriptions  
Pin Names  
OE1, OE2  
Description  
IEEE/IEC  
3-STATE Output Enable Inputs  
I0I7  
Inputs  
O0O7  
Outputs  
Truth Tables  
Inputs  
OE1  
Outputs  
In  
(Pins 12, 14, 16, 18)  
L
L
L
H
X
H
L
Connection Diagram  
H
Z
Inputs  
OE2  
Outputs  
In  
(Pins 3, 5, 7, 9)  
L
L
L
H
X
H
L
H
Z
H = HIGH Voltage Level  
X = Immaterial  
L = LOW Voltage Level  
Z = High Impedance  
© 2001 Fairchild Semiconductor Corporation  
DS011611  
www.fairchildsemi.com  

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