Datasheet > 74LVC3G17DC,125

74LVC3G17DC,125

更新时间： 2024-10-03 09:22:07

品牌	Logo	应用领域
恩智浦 - NXP		/
页数	文件大小	规格书
23页	285K
描述
74LVC3G17 - Triple non-inverting Schmitt trigger with 5 V tolerant input SSOP 8-Pin

阅读下载

中文翻译

获取价格

如果您发现信息不准确，欢迎纠错

74LVC3G17DC,125 数据手册

74LVC3G17

Triple non-inverting Schmitt trigger with 5 V tolerant input

Rev. 11 — 9 April 2013

Product data sheet

1. General description

The 74LVC3G17 provides three non-inverting buffers with Schmitt trigger input. It is

capable of transforming slowly changing input signals into sharply defined, jitter-free

output signals.

Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of the

74LVC3G17 as a translator in a mixed 3.3 V and 5 V environment.

This device is fully specified for partial power-down applications using I_OFF. The I_OFF

circuitry disables the output, preventing a damaging backflow current through the device

when it is powered down.

2. Features and benefits

 Wide supply voltage range from 1.65 V to 5.5 V

 5 V tolerant input/output for interfacing with 5 V logic

 High noise immunity

 ESD protection:

 HBM JESD22-A114F exceeds 2000 V

 MM JESD22-A115-A exceeds 200 V

 24 mA output drive (V_CC= 3.0 V)

 CMOS low-power consumption

 Latch-up performance exceeds 250 mA

 Direct interface with TTL levels

 Multiple package options

 Specified from 40 C to +85 C and 40 C to +125 C

3. Applications

 Wave and pulse shapers for highly noisy environments

12 3 4 5 6 7...23

中文翻译

下载PDF

型号	品牌	获取价格	描述	数据表
74LVC3G17DC,132	NXP	获取价格	Buffer, LVC/LCX/Z Series, 3-Func, 1-Input, CMOS, PDSO8
74LVC3G17DC-G	NXP	获取价格	Triple non-inverting Schmitt trigger with 5 V tolerant input - Description: Triple Schmitt
74LVC3G17DC-Q100	NXP	获取价格	IC NON-INVERT GATE, Gate
74LVC3G17DC-Q100	NEXPERIA	获取价格	Triple non-inverting Schmitt trigger with 5 V tolerant input
74LVC3G17DP	NXP	获取价格	Triple non-inverting Schmitt trigger with 5 V tolerant input
74LVC3G17DP	NEXPERIA	获取价格	Triple non-inverting Schmitt trigger with 5 V tolerant inputProduction
74LVC3G17DP-Q100	NEXPERIA	获取价格	Triple non-inverting Schmitt trigger with 5 V tolerant input
74LVC3G17DP-Q100,125	NXP	获取价格	Buffer, LVC/LCX/Z Series, 3-Func, 1-Input, CMOS, PDSO8
74LVC3G17GD	NXP	获取价格	Triple non-inverting Schmitt trigger with 5 V tolerant input
74LVC3G17GD,125	NXP	获取价格	74LVC3G17 - Triple non-inverting Schmitt trigger with 5 V tolerant input SON 8-Pin