Datasheet > 74LVC3G17DP-Q100,125

74LVC3G17DP-Q100,125

更新时间： 2024-10-03 08:25:55

品牌	Logo	应用领域
恩智浦 - NXP		光电二极管
页数	文件大小	规格书
16页	119K
描述
Buffer, LVC/LCX/Z Series, 3-Func, 1-Input, CMOS, PDSO8

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74LVC3G17DP-Q100,125 数据手册

74LVC3G17-Q100

Triple non-inverting Schmitt trigger with 5 V tolerant input

Rev. 1 — 22 May 2014

Product data sheet

1. General description

The 74LVC3G17-Q100 provides three non-inverting buffers with Schmitt trigger input. It is

capable of transforming slowly changing input signals into sharply defined, jitter-free

output signals.

Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of the

74LVC3G17-Q100 as a translator in a mixed 3.3 V and 5 V environment.

This device is fully specified for partial power-down applications using I_OFF. The I_OFF

circuitry disables the output, preventing a damaging backflow current through the device

when it is powered down.

This product has been qualified to the Automotive Electronics Council (AEC) standard

Q100 (Grade 1) and is suitable for use in automotive applications.

2. Features and benefits

 Automotive product qualification in accordance with AEC-Q100 (Grade 1)

 Specified from 40 C to +85 C and from 40 C to +125 C

 Wide supply voltage range from 1.65 V to 5.5 V

 5 V tolerant input/output for interfacing with 5 V logic

 High noise immunity

 ESD protection:

 MIL-STD-883, method 3015 exceeds 2000 V

 HBM JESD22-A114F exceeds 2000 V

 MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 )

 24 mA output drive (V_CC= 3.0 V)

 CMOS low-power consumption

 Latch-up performance exceeds 250 mA

 Direct interface with TTL levels

 Multiple package options

3. Applications

 Wave and pulse shapers for highly noisy environments

12 3 4 5 6 7...16

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型号	品牌	获取价格	描述	数据表
74LVC3G17GD	NXP	获取价格	Triple non-inverting Schmitt trigger with 5 V tolerant input
74LVC3G17GD,125	NXP	获取价格	74LVC3G17 - Triple non-inverting Schmitt trigger with 5 V tolerant input SON 8-Pin
74LVC3G17GF	NXP	获取价格	LVC/LCX/Z SERIES, TRIPLE 1-INPUT NON-INVERT GATE, PDSO8, 1.35 X 1 MM, 0.5 MM HEIGHT, MO-25
74LVC3G17GF,115	NXP	获取价格	74LVC3G17 - Triple non-inverting Schmitt trigger with 5 V tolerant input SON 8-Pin
74LVC3G17GM	NXP	获取价格	Triple non-inverting Schmitt trigger with 5 V tolerant input
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74LVC3G17GM-G	NXP	获取价格	IC,LOGIC GATE,TRIPLE BUFFER,LCX/LVC-CMOS,LLCC,8PIN,PLASTIC
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