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74LVC3G17GN PDF预览

74LVC3G17GN

更新时间: 2024-09-30 13:04:59
品牌 Logo 应用领域
恩智浦 - NXP 触发器
页数 文件大小 规格书
16页 89K
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74LVC3G17GN 数据手册

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74LVC3G17  
Triple non-inverting Schmitt trigger with 5 V tolerant input  
Rev. 03 — 31 January 2005  
Product data sheet  
1. General description  
The 74LVC3G17 is a high-performance, low-power, low-voltage, Si-gate CMOS device  
and superior to most advanced CMOS compatible TTL families.  
Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of this  
device as translator in a mixed 3.3 V and 5 V environment.  
This device is fully specified for partial power-down applications using Ioff. The Ioff circuitry  
disables the output, preventing the damaging backflow current through the device when it  
is powered down.  
The 74LVC3G17 provides three non-inverting buffers with Schmitt-trigger action. It is  
capable of transforming slowly changing input signals into sharply defined, jitter-free  
output signals.  
2. Features  
Wide supply voltage range from 1.65 V to 5.5 V  
5 V tolerant input/output for interfacing with 5 V logic  
High noise immunity  
ESD protection:  
HBM EIA/JESD22-A114-B exceeds 2000 V  
MM EIA/JESD22-A115-A exceeds 200 V.  
±24 mA output drive (VCC = 3.0 V)  
CMOS low power consumption  
Latch-up performance exceeds 250 mA  
Direct interface with TTL levels  
Multiple package options  
Specified from 40 °C to +85 °C and 40 °C to +125 °C.  
3. Applications  
Wave and pulse shapers for highly noisy environments.  

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