Datasheet > 74LVC3G17GT-G

74LVC3G17GT-G

更新时间： 2024-10-01 10:52:43

品牌	Logo	应用领域
恩智浦 - NXP		/
页数	文件大小	规格书
18页	102K
描述
Triple non-inverting Schmitt trigger with 5 V tolerant input

阅读下载

中文翻译

获取价格

如果您发现信息不准确，欢迎纠错

74LVC3G17GT-G 数据手册

74LVC3G17

Triple non-inverting Schmitt trigger with 5 V tolerant input

Rev. 06 — 6 June 2008

Product data sheet

1. General description

The 74LVC3G17 provides three non-inverting buffers with Schmitt trigger action. It is

capable of transforming slowly changing input signals into sharply deﬁned, jitter-free

output signals.

Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of the

74LVC3G17 as a translator in a mixed 3.3 V and 5 V environment.

This device is fully speciﬁed for partial power-down applications using I_OFF. The I_OFF

circuitry disables the output, preventing a damaging backﬂow current through the device

when it is powered down.

2. Features

I Wide supply voltage range from 1.65 V to 5.5 V

I 5 V tolerant input/output for interfacing with 5 V logic

I High noise immunity

I ESD protection:

N HBM JESD22-A114E exceeds 2000 V

N MM JESD22-A115-A exceeds 200 V

I ±24 mA output drive (V_CC= 3.0 V)

I CMOS low-power consumption

I Latch-up performance exceeds 250 mA

I Direct interface with TTL levels

I Multiple package options

I Speciﬁed from −40 °C to +85 °C and −40 °C to +125 °C

3. Applications

I Wave and pulse shapers for highly noisy environments

12 3 4 5 6 7...18

中文翻译

下载PDF

型号	品牌	获取价格	描述	数据表
74LVC3G17-Q100	NEXPERIA	获取价格	Triple non-inverting Schmitt trigger with 5 V tolerant input
74LVC3G34	NXP	获取价格	Triple buffer gate
74LVC3G34	DIODES	获取价格	Triple gate 1 Input Buffer
74LVC3G34_08	NXP	获取价格	Triple buffer
74LVC3G34DC	NXP	获取价格	Triple buffer gate
74LVC3G34DC	NEXPERIA	获取价格	Triple bufferProduction
74LVC3G34DC,125	NXP	获取价格	74LVC3G34 - Triple buffer SSOP 8-Pin
74LVC3G34DC-Q100	NEXPERIA	获取价格	Triple buffer
74LVC3G34DC-Q100H	NXP	获取价格	74LVC3G34-Q100 - Triple buffer SSOP 8-Pin
74LVC3G34DP	NXP	获取价格	Triple buffer gate