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74LVC1G53GM,125 PDF预览

74LVC1G53GM,125

更新时间: 2024-11-20 14:47:07
品牌 Logo 应用领域
恩智浦 - NXP /
页数 文件大小 规格书
27页 342K
描述
74LVC1G53 - 2-channel analog multiplexer/demultiplexer QFN 8-Pin

74LVC1G53GM,125 技术参数

Source Url Status Check Date:2013-06-14 00:00:00是否Rohs认证: 符合
生命周期:Transferred零件包装代码:QFN
包装说明:1.60 X 1.60 MM, 0.50 MM HEIGHT, PLASTIC, MO-255, SOT-902-1, XQFN-8针数:8
Reach Compliance Code:compliant风险等级:5.78
Base Number Matches:1

74LVC1G53GM,125 数据手册

 浏览型号74LVC1G53GM,125的Datasheet PDF文件第2页浏览型号74LVC1G53GM,125的Datasheet PDF文件第3页浏览型号74LVC1G53GM,125的Datasheet PDF文件第4页浏览型号74LVC1G53GM,125的Datasheet PDF文件第5页浏览型号74LVC1G53GM,125的Datasheet PDF文件第6页浏览型号74LVC1G53GM,125的Datasheet PDF文件第7页 
74LVC1G53  
2-channel analog multiplexer/demultiplexer  
Rev. 9 — 5 April 2013  
Product data sheet  
1. General description  
The 74LVC1G53 is a low-power, low-voltage, high-speed, Si-gate CMOS device.  
The 74LVC1G53 provides one analog multiplexer/demultiplexer with a digital select  
input (S), two independent inputs/outputs (Y0 and Y1), a common input/output (Z) and an  
active LOW enable input (E). When pin E is HIGH, the switch is turned off.  
Schmitt trigger action at the select and enable inputs makes the circuit tolerant of slower  
input rise and fall times across the entire VCC range from 1.65 V to 5.5 V.  
2. Features and benefits  
Wide supply voltage range from 1.65 V to 5.5 V  
Very low ON resistance:  
7.5 (typical) at VCC = 2.7 V  
6.5 (typical) at VCC = 3.3 V  
6 (typical) at VCC = 5 V  
Switch current capability of 32 mA  
High noise immunity  
CMOS low power consumption  
TTL interface compatibility at 3.3 V  
Latch-up performance meets requirements of JESD 78 Class I  
ESD protection:  
HBM JESD22-A114F exceeds 2000 V  
MM JESD22-A115-A exceeds 200 V  
CDM JESD22-C101E exceeds 1000 V  
Control inputs accept voltages up to 5 V  
Multiple package options  
Specified from 40 C to +85 C and from 40 C to +125 C  
 
 

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