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74LVC1G157GS,132 PDF预览

74LVC1G157GS,132

更新时间: 2024-11-18 15:28:07
品牌 Logo 应用领域
恩智浦 - NXP /
页数 文件大小 规格书
18页 196K
描述
74LVC1G157 - Single 2-input multiplexer

74LVC1G157GS,132 技术参数

Source Url Status Check Date:2013-06-14 00:00:00是否Rohs认证: 符合
生命周期:Transferred包装说明:1 X 1 MM, 0.35 MM HEIGHT, SOT-1202, SON-6
Reach Compliance Code:compliant风险等级:5.77
Base Number Matches:1

74LVC1G157GS,132 数据手册

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74LVC1G157  
Single 2-input multiplexer  
Rev. 6 — 31 December 2012  
Product data sheet  
1. General description  
The 74LVC1G157 is a single 2-input multiplexer which select data from two data inputs (I0  
and I1) under control of a common data select input (S). The state of the common data  
select input determines the particular register from which the data comes. The output (Y)  
presents the selected data in the true (non-inverted) form.  
Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these  
devices as translators in mixed 3.3 V and 5 V applications.  
This device is fully specified for partial power-down applications using IOFF  
.
The IOFF circuitry disables the output, preventing the damaging backflow current through  
the device when it is powered down.  
Schmitt-trigger action at all inputs makes the circuit highly tolerant to slower input rise and  
fall times.  
2. Features and benefits  
Wide supply voltage range from 1.65 V to 5.5 V  
High noise immunity  
Complies with JEDEC standard:  
JESD8-7 (1.65 V to 1.95 V)  
JESD8-5 (2.3 V to 2.7 V)  
JESD8B/JESD36 (2.7 V to 3.6 V)  
24 mA output drive (VCC = 3.0 V)  
CMOS low power consumption  
Latch-up performance exceeds 250 mA  
Direct interface with TTL levels  
Inputs accept voltages up to 5 V  
ESD protection:  
HBM JESD22-A114F exceeds 2000 V  
MM JESD22-A115-A exceeds 200 V  
Multiple package options  
Specified from 40 C to +85 C and 40 C to +125 C  
 
 

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