Datasheet > 74LVC1G16GM

74LVC1G16GM

更新时间： 2024-11-10 01:07:03

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74LVC1G16GM 数据手册

74LVC1G16

Single buffer

Rev. 2 — 12 October 2016

Product data sheet

1. General description

The 74LVC1G16 provides a low-power, low-voltage single buffer.

The input can be driven from either 3.3 V or 5 V devices. This feature allows the use of

this device in a mixed 3.3 V and 5 V environment.

This device is fully specified for partial power-down applications using I_OFF. The I_OFF

circuitry disables the output, preventing the damaging backflow current through the device

when it is powered down.

Schmitt trigger action at all inputs makes the circuit highly tolerant of slower input rise and

fall times.

2. Features and benefits

 Wide supply voltage range from 1.65 V to 5.5 V

 5 V tolerant inputs for interfacing with 5 V logic

 High noise immunity

 Complies with JEDEC standard:

 JESD8-7 (1.65 V to 1.95 V)

 JESD8-5 (2.3 V to 2.7 V)

 JESD8-B/JESD36 (2.7 V to 3.6 V).

 ESD protection:

 HBM JESD22-A114F exceeds 2000 V

 MM JESD22-A115-A exceeds 200 V

 24 mA output drive (V_CC= 3.0 V)

 CMOS low power consumption

 Latch-up performance exceeds 250 mA

 Direct interface with TTL levels

 Inputs accept voltages up to 5 V

 Multiple package options

 Specified from 40 C to +85 C and 40 C to +125 C

12 3 4 5 6 7...14

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型号	品牌	获取价格	描述	数据表
74LVC1G16GW	NEXPERIA	获取价格	Single buffer
74LVC1G16GW-Q100	NEXPERIA	获取价格	Single bufferProduction
74LVC1G17	DIODES	获取价格	SINGLE SCHMITT-TRIGGER BUFFER
74LVC1G17	NXP	获取价格	Single Schmitt-trigger buffer
74LVC1G17_1107	DIODES	获取价格	SINGLE SCHMITT-TRIGGER BUFFER
74LVC1G17_12	NXP	获取价格	Single Schmitt trigger buffer
74LVC1G175	NXP	获取价格	Single D-type flip-flop with reset; positive-edge trigger
74LVC1G175DBVRE4	TI	获取价格	具有异步清零功能的单路 D 型触发器 \| DBV \| 6 \| -40 to 125
74LVC1G175DBVRG4	TI	获取价格	具有异步清零功能的单路 D 型触发器 \| DBV \| 6 \| -40 to 125
74LVC1G175DCKRG4	TI	获取价格	具有异步清零功能的单路 D 型触发器 \| DCK \| 6 \| -40 to 125