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74LCX74MTC_NL PDF预览

74LCX74MTC_NL

更新时间: 2024-11-07 13:04:59
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 触发器
页数 文件大小 规格书
11页 529K
描述
D Flip-Flop, LVC/LCX/Z Series, 2-Func, Positive Edge Triggered, 1-Bit, Complementary Output, CMOS, PDSO14, 4.40 MM, LEAD FREE, MO-153AB, TSSOP-14

74LCX74MTC_NL 技术参数

生命周期:Obsolete零件包装代码:TSSOP
包装说明:TSSOP,针数:14
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.66Is Samacsys:N
系列:LVC/LCX/ZJESD-30 代码:R-PDSO-G14
JESD-609代码:e3长度:5 mm
逻辑集成电路类型:D FLIP-FLOP位数:1
功能数量:2端子数量:14
最高工作温度:85 °C最低工作温度:-40 °C
输出极性:COMPLEMENTARY封装主体材料:PLASTIC/EPOXY
封装代码:TSSOP封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH传播延迟(tpd):8.4 ns
认证状态:Not Qualified座面最大高度:1.2 mm
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):2 V
标称供电电压 (Vsup):2.5 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:MATTE TIN端子形式:GULL WING
端子节距:0.65 mm端子位置:DUAL
触发器类型:POSITIVE EDGE宽度:4.4 mm
最小 fmax:150 MHzBase Number Matches:1

74LCX74MTC_NL 数据手册

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March 1995  
Revised February 2005  
74LCX74  
Low Voltage Dual D-Type Positive  
Edge-Triggered Flip-Flop with 5V Tolerant Inputs  
General Description  
Features  
5V tolerant inputs  
The LCX74 is a dual D-type flip-flop with Asynchronous  
Clear and Set inputs and complementary (Q, Q) outputs.  
Information at the input is transferred to the outputs on the  
positive edge of the clock pulse. After the Clock Pulse input  
threshold voltage has been passed, the Data input is  
locked out and information present will not be transferred to  
the outputs until the next rising edge of the Clock Pulse  
input.  
2.3V–3.6V VCC specifications provided  
7.0 ns tPD max (VCC 3.3V), 10 A ICC max  
Power down high impedance inputs and outputs  
24 mA output drive (VCC 3.0V)  
Implements patented noise/EMI reduction circuitry  
Latch-up performance exceeds JEDEC 78 conditions  
ESD performance:  
Asynchronous Inputs:  
LOW input to SD (Set) sets Q to HIGH level  
Human body model 2000V  
LOW input to CD (Clear) sets Q to LOW level  
Machine model 200V  
Clear and Set are independent of clock  
Simultaneous LOW on CD and SD makes both Q and  
Q HIGH  
Leadless Pb-Free DQFN package  
Ordering Code:  
Package  
Order Number  
Package Description  
Number  
74LCX74M  
M14A  
M14A  
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow  
74LCX74MX_NL  
(Note 2)  
Pb-Free 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow  
74LCX74SJ  
M14D  
Pb-Free 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide  
74LCX74BQX  
(Note 1)  
MLP014A Pb-Free 14-Terminal Depopulated Quad Very-Thin Flat Pack No Leads (DQFN), JEDEC  
MO-241, 2.5 x 3.0mm  
74LCX74MTC  
MTC14  
MTC14  
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide  
74LCX74MTCX_NL  
(Note 2)  
Pb-Free 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm  
Wide  
Devices also available in Tape and Reel. Specify by appending the suffix letter Xto the ordering code.  
Pb-Free package per JEDEC J-STD-020B.  
Note 1: DQFN package available in Tape and Reel only.  
Note 2: _NLindicates Pb-Free package (per JEDEC J-STD-020B). Device available in Tape and Reel only.  
© 2005 Fairchild Semiconductor Corporation  
DS012414  
www.fairchildsemi.com  

74LCX74MTC_NL 替代型号

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