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74LCX74MTCX PDF预览

74LCX74MTCX

更新时间: 2024-11-07 12:26:59
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 触发器锁存器逻辑集成电路光电二极管
页数 文件大小 规格书
13页 826K
描述
74LCX74 Low Voltage Dual D-Type Positive Edge-Triggered Flip-Flop with 5V Tolerant Inputs

74LCX74MTCX 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Transferred零件包装代码:TSSOP
包装说明:TSSOP, TSSOP14,.25针数:14
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.24
系列:LVC/LCX/ZJESD-30 代码:R-PDSO-G14
JESD-609代码:e4长度:5 mm
负载电容(CL):50 pF逻辑集成电路类型:D FLIP-FLOP
最大频率@ Nom-Sup:150000000 Hz最大I(ol):0.024 A
湿度敏感等级:1位数:1
功能数量:2端子数量:14
最高工作温度:85 °C最低工作温度:-40 °C
输出极性:COMPLEMENTARY封装主体材料:PLASTIC/EPOXY
封装代码:TSSOP封装等效代码:TSSOP14,.25
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
包装方法:TAPE AND REEL峰值回流温度(摄氏度):260
电源:3.3 VProp。Delay @ Nom-Sup:7 ns
传播延迟(tpd):8.4 ns认证状态:Not Qualified
座面最大高度:1.2 mm子类别:FF/Latches
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):2 V
标称供电电压 (Vsup):2.5 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)端子形式:GULL WING
端子节距:0.65 mm端子位置:DUAL
处于峰值回流温度下的最长时间:30触发器类型:POSITIVE EDGE
宽度:4.4 mm最小 fmax:150 MHz
Base Number Matches:1

74LCX74MTCX 数据手册

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March 2008  
74LCX74  
Low Voltage Dual D-Type Positive Edge-Triggered  
Flip-Flop with 5V Tolerant Inputs  
Features  
General Description  
5V tolerant inputs  
The LCX74 is a dual D-type flip-flop with Asynchronous  
Clear and Set inputs and complementary (Q, Q) outputs.  
Information at the input is transferred to the outputs on  
the positive edge of the clock pulse. After the Clock  
Pulse input threshold voltage has been passed, the Data  
input is locked out and information present will not be  
transferred to the outputs until the next rising edge of the  
Clock Pulse input.  
2.3V–3.6V V specifications provided  
CC  
7.0ns t max. (V = 3.3V), 10µA I max.  
PD  
CC  
CC  
Power down high impedance inputs and outputs  
24mA output drive (V = 3.0V)  
CC  
Implements proprietary noise/EMI reduction circuitry  
Latch-up performance exceeds JEDEC 78 conditions  
ESD performance:  
Asynchronous Inputs:  
– Human body model > 2000V  
LOW input to S (Set) sets Q to HIGH level  
D
– Machine model > 200V  
LOW input to C (Clear) sets Q to LOW level  
D
Leadless Pb-Free DQFN package  
Clear and Set are independent of clock  
Simultaneous LOW on C and S makes both Q  
D
D
and Q HIGH  
Ordering Information  
Package  
Order Number  
Number  
Package Description  
74LCX74M  
M14A  
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150"  
Narrow  
74LCX74SJ  
M14D  
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide  
(1)  
74LCX74BQX  
MLP14A  
14-Terminal Depopulated Quad Very-Thin Flat Pack No Leads (DQFN),  
JEDEC MO-241, 2.5 x 3.0mm  
74LCX74MTC  
MTC14  
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153,  
4.4mm Wide  
Note:  
1. DQFN package available in Tape and Reel only.  
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number.  
All packages are lead free per JEDEC: J-STD-020B standard.  
©1995 Fairchild Semiconductor Corporation  
74LCX74 Rev. 1.7.0  
www.fairchildsemi.com  

74LCX74MTCX 替代型号

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74LCX74MTC ONSEMI

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