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74LCX760WM PDF预览

74LCX760WM

更新时间: 2024-11-06 22:35:07
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 总线驱动器总线收发器逻辑集成电路光电二极管
页数 文件大小 规格书
10页 101K
描述
Low Voltage Buffer/Line Driver with 5V Tolerant Inputs and Open Drain Outputs

74LCX760WM 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Transferred零件包装代码:SOIC
包装说明:SOP, SOP20,.4针数:20
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.57
Is Samacsys:N控制类型:ENABLE LOW
系列:LVC/LCX/ZJESD-30 代码:R-PDSO-G20
JESD-609代码:e3长度:12.8 mm
逻辑集成电路类型:BUS DRIVER最大I(ol):0.024 A
湿度敏感等级:1位数:8
功能数量:1端口数量:2
端子数量:20最高工作温度:85 °C
最低工作温度:-40 °C输出特性:OPEN-DRAIN
输出极性:TRUE封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装等效代码:SOP20,.4
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
包装方法:RAIL峰值回流温度(摄氏度):260
电源:3.3 VProp。Delay @ Nom-Sup:8 ns
传播延迟(tpd):10 ns认证状态:Not Qualified
座面最大高度:2.65 mm子类别:Bus Driver/Transceivers
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):2 V
标称供电电压 (Vsup):2.5 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:Matte Tin (Sn)端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:7.5 mm
Base Number Matches:1

74LCX760WM 数据手册

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July 2001  
Revised February 2002  
74LCX760  
Low Voltage Buffer/Line Driver  
with 5V Tolerant Inputs and Open Drain Outputs  
General Description  
Features  
Open drain version of the LCX244  
The LCX760 is the Open Drain version of the LCX244. The  
LCX760 contains eight non-inverting buffers with 3-STATE  
outputs. The device may be employed as a memory  
address driver, clock driver and bus-oriented transmitter/  
receiver. The LCX760 is designed for low voltage (2.5V or  
3.3V) VCC applications with capability of interfacing to a 5V  
5V tolerant inputs and outputs  
2.3V–3.6V VCC specifications provided  
8.0 ns tPD max (VCC = 3.3V), 10 µA ICC max  
Power down high impedance inputs and outputs  
Supports live insertion/withdrawal (Note 1)  
24 mA output drive (VCC = 3.0V)  
signal environment.  
The LCX760 is fabricated with an advanced CMOS tech-  
nology to achieve high speed operation while maintaining  
CMOS low power dissipation.  
Implements patented noise/EMI reduction circuitry  
Latch-up conforms to JEDEC JED78  
ESD performance:  
Human body model > 2000V  
Machine model > 200V  
Note 1: To ensure the high-impedance state during power up or down, OE  
should be tied to VCC through a pull-up resistor: the minimum value or the  
resistor is determined by the current-sourcing capability of the driver.  
Ordering Code:  
Order Number Package Number  
Package Description  
74LCX760WM  
74LCX760SJ  
M20B  
M20D  
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300Wide  
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 4.4mm Wide  
74LCX760MSA  
74LCX760MTC  
MSA20  
MTC20  
20-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide  
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide  
Devices also available in Tape and Reel. Specify by appending the suffix letter Xto the ordering code.  
Logic Symbol  
Connection Diagram  
IEEE/IEC  
© 2002 Fairchild Semiconductor Corporation  
DS500413  
www.fairchildsemi.com  

74LCX760WM 替代型号

型号 品牌 替代类型 描述 数据表
74LCX760WMX FAIRCHILD

完全替代

BUFFER/DRIVER|DUAL|4-BIT|LCX-CMOS|SOP|20PIN|PLASTIC
74LCX760MTCX FAIRCHILD

完全替代

BUFFER/DRIVER|DUAL|4-BIT|LCX-CMOS|TSSOP|20PIN|PLASTIC
74LCX760MTC FAIRCHILD

完全替代

Low Voltage Buffer/Line Driver with 5V Tolerant Inputs and Open Drain Outputs

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