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74HCT259N,652 PDF预览

74HCT259N,652

更新时间: 2024-11-20 14:47:03
品牌 Logo 应用领域
恩智浦 - NXP 光电二极管逻辑集成电路触发器
页数 文件大小 规格书
22页 174K
描述
74HC(T)259 - 8-bit addressable latch DIP 16-Pin

74HCT259N,652 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:DIP包装说明:DIP, DIP16,.3
针数:16Reach Compliance Code:compliant
ECCN代码:EAR99HTS代码:8542.39.00.01
风险等级:7.8其他特性:1:8 DMUX FOLLOWED BY LATCH
系列:HCTJESD-30 代码:R-PDIP-T16
JESD-609代码:e4长度:21.6 mm
负载电容(CL):50 pF逻辑集成电路类型:D LATCH
最大I(ol):0.004 A位数:1
功能数量:1端子数量:16
最高工作温度:125 °C最低工作温度:-40 °C
输出极性:TRUE封装主体材料:PLASTIC/EPOXY
封装代码:DIP封装等效代码:DIP16,.3
封装形状:RECTANGULAR封装形式:IN-LINE
峰值回流温度(摄氏度):260电源:5 V
Prop。Delay @ Nom-Sup:59 ns传播延迟(tpd):57 ns
认证状态:Not Qualified座面最大高度:4.7 mm
子类别:FF/Latches最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:NO技术:CMOS
温度等级:AUTOMOTIVE端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式:THROUGH-HOLE端子节距:2.54 mm
端子位置:DUAL处于峰值回流温度下的最长时间:30
触发器类型:LOW LEVEL宽度:7.62 mm
Base Number Matches:1

74HCT259N,652 数据手册

 浏览型号74HCT259N,652的Datasheet PDF文件第2页浏览型号74HCT259N,652的Datasheet PDF文件第3页浏览型号74HCT259N,652的Datasheet PDF文件第4页浏览型号74HCT259N,652的Datasheet PDF文件第5页浏览型号74HCT259N,652的Datasheet PDF文件第6页浏览型号74HCT259N,652的Datasheet PDF文件第7页 
74HC259; 74HCT259  
8-bit addressable latch  
Rev. 5 — 7 August 2012  
Product data sheet  
1. General description  
The 74HC259; 74HCT259 are high-speed Si-gate CMOS devices and are pin compatible  
with Low-power Schottky TTL (LSTTL). They are specified in compliance with JEDEC  
standard No. 7-A.  
The 74HC259; 74HCT259 are high-speed 8-bit addressable latches designed for  
general-purpose storage applications in digital systems. They are multifunctional devices  
capable of storing single-line data in eight addressable latches. They provide a 3-to-8  
decoder and multiplexer function with active HIGH outputs (Q0 to Q7). They also  
incorporate an active LOW common reset (MR) for resetting all latches as well as an  
active LOW enable input (LE).  
The 74HC259; 74HCT259 has four modes of operation:  
Addressable latch mode, in this mode data on the data line (D) is written into the  
addressed latch. The addressed latch follows the data input with all non-addressed  
latches remaining in their previous states.  
Memory mode, in this mode all latches remain in their previous states and are  
unaffected by the data or address inputs.  
Demultiplexing mode (or 3-to-8 decoding), in this mode the addressed output follows  
the state of the data input (D) with all other outputs in the LOW state.  
Reset mode, in this mode all outputs are LOW and unaffected by the address inputs  
(A0 to A2) and data input (D).  
When operating the 74HC259; 74HCT259 as an address latch, changing more than one  
address bit could impose a transient wrong address. Therefore, this should only be done  
while in the Memory mode.  
2. Features and benefits  
Combined demultiplexer and 8-bit latch  
Serial-to-parallel capability  
Output from each storage bit available  
Random (addressable) data entry  
Easily expandable  
Common reset input  
Useful as a 3-to-8 active HIGH decoder  
Input levels:  
For 74HC259: CMOS level  
For 74HCT259: TTL level  
 
 

74HCT259N,652 替代型号

型号 品牌 替代类型 描述 数据表
74HCT259PW,118 NXP

完全替代

74HC(T)259 - 8-bit addressable latch TSSOP 16-Pin
74HCT259D,653 NXP

完全替代

74HC(T)259 - 8-bit addressable latch SOP 16-Pin

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