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74HCT259PW-Q100 PDF预览

74HCT259PW-Q100

更新时间： 2024-11-20 12:50:43
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恩智浦 - NXP 触发器锁存器逻辑集成电路光电二极管
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描述
8-bit addressable latch

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74HCT259PW-Q100 数据手册

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74HC259-Q100; 74HCT259-Q100  
8-bit addressable latch  
Rev. 1 — 30 July 2012  
Product data sheet  
1. General description  
The 74HC259-Q100; 74HCT259-Q100 are high-speed Si-gate CMOS devices and are pin  
compatible with Low-power Schottky TTL (LSTTL). They are specified in compliance with  
JEDEC standard No. 7A.  
The 74HC259-Q100; 74HCT259-Q100 are high-speed 8-bit addressable latches  
designed for general-purpose storage applications in digital systems. They are  
multifunctional devices capable of storing single-line data in eight addressable latches and  
providing a 3-to-8 decoder and multiplexer function with active HIGH outputs (Q0 to Q7).  
They also incorporate an active LOW common reset (MR) for resetting all latches as well  
as an active LOW enable input (LE).  
The 74HC259-Q100; 74HCT259-Q100 has four modes of operation:  
• Addressable latch mode, in this mode data on the data line (D) is written into the  
addressed latch. The addressed latch follows the data input with all non-addressed  
latches remaining in their previous states.  
• Memory mode, in this mode all latches remain in their previous states and are  
unaffected by the data or address inputs.  
• Demultiplexing mode (or 3-to-8 decoding), in this mode the addressed output follows  
the state of the data input (D) with all other outputs in the LOW state.  
• Reset mode, in this mode all outputs are LOW and unaffected by the address inputs  
(A0 to A2) and data input (D).  
When operating the 74HC259-Q100; 74HCT259-Q100 as an address latch, changing  
more than one address bit could impose a transient wrong address. Therefore, this should  
only be done while in the Memory mode.  
This product has been qualified to the Automotive Electronics Council (AEC) standard  
Q100 (Grade 1) and is suitable for use in automotive applications.  
2. Features and benefits  
Automotive product qualification in accordance with AEC-Q100 (Grade 1)  
Specified from 40 C to +85 C and from 40 C to +125 C  
Combined demultiplexer and 8-bit latch  
Serial-to-parallel capability  
Output from each storage bit available  
Random (addressable) data entry  
Easily expandable  
Common reset input  
1234567...20

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