Datasheet > 74HC73PW

74HC73PW

更新时间： 2024-11-12 11:12:19

品牌	Logo	应用领域
安世 - NEXPERIA		光电二极管逻辑集成电路触发器
页数	文件大小	规格书
13页	240K
描述
Dual JK flip-flop with reset; negative-edge triggerProduction

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74HC73PW 数据手册

74HC73

Dual JK flip-flop with reset; negative-edge trigger

Rev. 7 — 13 September 2021

Product data sheet

1. General description

The 74HC73 is a dual negative edge triggered JK flip-flop with individual J, K, clock (nCP) and

reset (nR) inputs and complementary nQ and nQ outputs. The J and K inputs must be stable

one set-up time prior to the HIGH-to-LOW clock transition for predictable operation. (nR) is

asynchronous, when LOW it overrides the clock and data inputs, forcing the nQ output LOW and

the nQ output HIGH. Schmitt-trigger action in the clock input makes the circuit highly tolerant

to slower clock rise and fall times. Inputs include clamp diodes. This enables the use of current

limiting resistors to interface inputs to voltages in excess of V_CC

2. Features and benefits

•

CMOS low-power dissipation

•

Wide supply voltage range from 2.0 to 6.0 V

High noise immunity

Latch-up performance exceeds 100 mA per JESD 78 Class II Level B

Complies with JEDEC standards

•

JESD8C (2.7 V to 3.6 V)

JESD7A (2.0 V to 6.0 V)

•

ESD protection:

•

HBM JESD22-A114F exceeds 2000 V

MM JESD22-A115-A exceeds 200 V

Specified from -40 °C to +80 °C and from -40 °C to +125 °C

3. Ordering information

Table 1. Ordering information

Type number Package

Temperature range Name

Description

Version

74HC73D

-40 °C to +125 °C

SO14

plastic small outline package; 14 leads;

body width 3.9 mm

SOT108-1

74HC73PW

-40 °C to +125 °C

TSSOP14 plastic thin shrink small outline package; 14 leads;

body width 4.4 mm

SOT402-1

12 3 4 5 6 7...13

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