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74HC164D/T3 PDF预览

74HC164D/T3

更新时间: 2024-11-01 21:09:47
品牌 Logo 应用领域
恩智浦 - NXP 光电二极管输出元件逻辑集成电路触发器
页数 文件大小 规格书
24页 131K
描述
IC HC/UH SERIES, 8-BIT RIGHT SERIAL IN PARALLEL OUT SHIFT REGISTER, TRUE OUTPUT, PDSO14, 3.90 MM, PLASTIC, MS-012, SOT-108-2, SOP-14, Shift Register

74HC164D/T3 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:SOIC
包装说明:SOP,针数:14
Reach Compliance Code:compliantHTS代码:8542.39.00.01
风险等级:5.08计数方向:RIGHT
系列:HC/UHJESD-30 代码:R-PDSO-G14
JESD-609代码:e4长度:8.65 mm
逻辑集成电路类型:SERIAL IN PARALLEL OUT湿度敏感等级:1
位数:8功能数量:1
端子数量:14最高工作温度:125 °C
最低工作温度:-40 °C输出极性:TRUE
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
峰值回流温度(摄氏度):260传播延迟(tpd):255 ns
认证状态:Not Qualified座面最大高度:1.75 mm
最大供电电压 (Vsup):6 V最小供电电压 (Vsup):2 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:CMOS温度等级:AUTOMOTIVE
端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
处于峰值回流温度下的最长时间:30触发器类型:POSITIVE EDGE
宽度:3.9 mm最小 fmax:24 MHz
Base Number Matches:1

74HC164D/T3 数据手册

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74HC164; 74HCT164  
8-bit serial-in, parallel-out shift register  
Rev. 03 — 4 April 2005  
Product data sheet  
1. General description  
The 74HC164; 74HCT164 are high-speed Si-gate CMOS devices and are pin compatible  
with Low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC  
standard no. 7A.  
The 74HC164; 74HCT164 are 8-bit edge-triggered shift registers with serial data entry  
and an output from each of the eight stages. Data is entered serially through one of two  
inputs (DSA or DSB); either input can be used as an active HIGH enable for data entry  
through the other input. Both inputs must be connected together or an unused input must  
be tied HIGH.  
Data shifts one place to the right on each LOW-to-HIGH transition of the clock (CP) input  
and enters into Q0, which is the logical AND of the two data inputs (DSA and DSB) that  
existed one set-up time prior to the rising clock edge.  
A LOW level on the master reset (MR) input overrides all other inputs and clears the  
register asynchronously, forcing all outputs LOW.  
2. Features  
Gated serial data inputs  
Asynchronous master reset  
Complies with JEDEC standard no. 7A  
ESD protection:  
HBM EIA/JESD22-A114-B exceeds 2000 V  
MM EIA/JESD22-A115-A exceeds 200 V.  
Multiple package options  
Specified from 40 °C to +85 °C and 40 °C to +125 °C.  
3. Quick reference data  
Table 1:  
Quick reference data  
GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns.  
Symbol  
Parameter  
Conditions  
Min  
Typ  
Max  
Unit  
Type 74HC164  
tPHL, tPLH  
propagation delay  
CP to Qn  
CL = 15 pF;  
-
-
12  
11  
-
-
ns  
ns  
V
CC = 5 V  
CL = 15 pF;  
CC = 5 V  
MR to Qn  
V

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