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74HC164-Q100 PDF预览

74HC164-Q100

更新时间: 2024-11-21 01:07:43
品牌 Logo 应用领域
安世 - NEXPERIA /
页数 文件大小 规格书
18页 725K
描述
8-bit serial-in, parallel-out shift register

74HC164-Q100 数据手册

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74HC164-Q100; 74HCT164-Q100  
8-bit serial-in, parallel-out shift register  
Rev. 1 — 16 August 2013  
Product data sheet  
1. General description  
The 74HC164-Q100; 74HCT164-Q100 is an 8-bit serial-in/parallel-out shift register. The  
device features two serial data inputs (DSA and DSB), eight parallel data outputs (Q0 to  
Q7). Data is entered serially through DSA or DSB and either input can be used as an  
active HIGH enable for data entry through the other input. Data is shifted on the  
LOW-to-HIGH transitions of the clock (CP) input. A LOW on the master reset input (MR)  
clears the register and forces all outputs LOW, independently of other inputs. Inputs  
include clamp diodes that enable the use of current limiting resistors to interface inputs to  
voltages in excess of VCC  
.
This product has been qualified to the Automotive Electronics Council (AEC) standard  
Q100 (Grade 1) and is suitable for use in automotive applications.  
2. Features and benefits  
Automotive product qualification in accordance with AEC-Q100 (Grade 1)  
Specified from 40 C to +85 C and from 40 C to +125 C  
Input levels:  
For 74HC164-Q100: CMOS level  
For 74HCT164-Q100: TTL level  
Gated serial data inputs  
Asynchronous master reset  
Complies with JEDEC standard no. 7A  
ESD protection:  
MIL-STD-883, method 3015 exceeds 2000 V  
HBM JESD22-A114F exceeds 2000 V  
MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 )  
Multiple package options  

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