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74HC165PW PDF预览

74HC165PW

更新时间: 2024-11-03 11:11:59
品牌 Logo 应用领域
安世 - NEXPERIA 光电二极管逻辑集成电路触发器
页数 文件大小 规格书
18页 290K
描述
8-bit parallel-in/serial out shift registerProduction

74HC165PW 数据手册

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74HC165; 74HCT165  
8-bit parallel-in/serial out shift register  
Rev. 7 — 1 September 2021  
Product data sheet  
1. General description  
The 74HC165; 74HCT165 are 8-bit serial or parallel-in/serial-out shift registers. The device  
features a serial data input (DS), eight parallel data inputs (D0 to D7) and two complementary  
serial outputs (Q7 and Q7). When the parallel load input (PL) is LOW the data from D0 to D7 is  
loaded into the shift register asynchronously. When PL is HIGH data enters the register serially at  
DS. When the clock enable input (CE) is LOW data is shifted on the LOW-to-HIGH transitions of  
the CP input. A HIGH on CE will disable the CP input. Inputs are overvoltage tolerant to 15 V. This  
enables the device to be used in HIGH-to-LOW level shifting applications.  
2. Features and benefits  
Wide supply voltage range from 2.0 to 6.0 V  
CMOS low power dissipation  
High noise immunity  
Latch-up performance exceeds 100 mA per JESD 78 Class II Level B  
Asynchronous 8-bit parallel load  
Synchronous serial input  
Input levels:  
For 74HC165: CMOS level  
For 74HCT165: TTL level  
Complies with JEDEC standards:  
JESD8C (2.7 V to 3.6 V)  
JESD7A (2.0 V to 6.0 V)  
ESD protection:  
HBM JESD22-A114F exceeds 2000 V  
MM JESD22-A115-A exceeds 200 V  
Multiple package options  
Specified from -40 °C to +85 °C and from -40 °C to +125 °C  
3. Applications  
Parallel-to-serial data conversion  
 
 
 

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