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74HC165BQ-Q100 PDF预览

74HC165BQ-Q100

更新时间: 2024-11-24 14:50:03
品牌 Logo 应用领域
恩智浦 - NXP 输出元件
页数 文件大小 规格书
21页 304K
描述
HC/UH SERIES, 8-BIT RIGHT PARALLEL IN SERIAL OUT SHIFT REGISTER, COMPLEMENTARY OUTPUT, PQCC16, 2.50 X 3.50 MM, 0.85 MM HEIGHT, PLASTIC, MO-241, SOT763-1, DHVQFN-16

74HC165BQ-Q100 技术参数

是否Rohs认证: 符合生命周期:Transferred
零件包装代码:QFN包装说明:2.50 X 3.50 MM, 0.85 MM HEIGHT, PLASTIC, MO-241, SOT763-1, DHVQFN-16
针数:16Reach Compliance Code:unknown
HTS代码:8542.39.00.01风险等级:5.57
计数方向:RIGHT系列:HC/UH
JESD-30 代码:R-PQCC-N16长度:3.5 mm
逻辑集成电路类型:PARALLEL IN SERIAL OUT湿度敏感等级:1
位数:8功能数量:1
端子数量:16最高工作温度:125 °C
最低工作温度:-40 °C输出极性:COMPLEMENTARY
封装主体材料:PLASTIC/EPOXY封装代码:HVQCCN
封装形状:RECTANGULAR封装形式:CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
峰值回流温度(摄氏度):260传播延迟(tpd):250 ns
筛选级别:AEC-Q100座面最大高度:1 mm
最大供电电压 (Vsup):6 V最小供电电压 (Vsup):2 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:CMOS温度等级:AUTOMOTIVE
端子形式:NO LEAD端子节距:0.5 mm
端子位置:QUAD处于峰值回流温度下的最长时间:30
触发器类型:POSITIVE EDGE宽度:2.5 mm
最小 fmax:24 MHzBase Number Matches:1

74HC165BQ-Q100 数据手册

 浏览型号74HC165BQ-Q100的Datasheet PDF文件第2页浏览型号74HC165BQ-Q100的Datasheet PDF文件第3页浏览型号74HC165BQ-Q100的Datasheet PDF文件第4页浏览型号74HC165BQ-Q100的Datasheet PDF文件第5页浏览型号74HC165BQ-Q100的Datasheet PDF文件第6页浏览型号74HC165BQ-Q100的Datasheet PDF文件第7页 
74HC165-Q100; 74HCT165-Q100  
8-bit parallel-in/serial out shift register  
Rev. 1 — 17 July 2012  
Product data sheet  
1. General description  
The 74HC165-Q100; 74HCT165-Q100 are high-speed Si-gate CMOS devices that  
comply with JEDEC standard no. 7A. They are pin compatible with Low-power Schottky  
TTL (LSTTL).  
The 74HC165-Q100; 74HCT165-Q100 are 8-bit parallel-load or serial-in shift registers  
with complementary serial outputs (Q7 and Q7) available from the last stage. When the  
parallel load (PL) input is LOW, parallel data from the D0 to D7 inputs are loaded into the  
register asynchronously.  
When PL is HIGH, data enters the register serially at the DS input and shifts one place to  
the right (Q0 Q1 Q2, etc.) with each positive-going clock transition. This feature  
allows parallel-to-serial converter expansion by tying the Q7 output to the DS input of the  
succeeding stage.  
The clock input is a gated-OR structure which allows one input to be used as an active  
LOW clock enable (CE) input. The pin assignment for the CP and CE inputs is arbitrary  
and can be reversed for layout convenience. The LOW-to-HIGH transition of input CE  
should only take place while CP HIGH for predictable operation. Either the CP or the CE  
should be HIGH before the LOW-to-HIGH transition of PL to prevent shifting the data  
when PL is activated.  
This product has been qualified to the Automotive Electronics Council (AEC) standard  
Q100 (Grade 1) and is suitable for use in automotive applications.  
2. Features and benefits  
Automotive product qualification in accordance with AEC-Q100 (Grade 1)  
Specified from 40 C to +85 C and from 40 C to +125 C  
Asynchronous 8-bit parallel load  
Synchronous serial input  
Complies with JEDEC standard no. 7A  
ESD protection:  
MIL-STD-883, method 3015 exceeds 2000 V  
HBM JESD22-A114F exceeds 2000 V  
MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 )  
Multiple package options  
3. Applications  
Parallel-to-serial data conversion  
 
 
 

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