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74HC164PW PDF预览

74HC164PW

更新时间: 2024-11-19 22:45:59
品牌 Logo 应用领域
恩智浦 - NXP 移位寄存器
页数 文件大小 规格书
24页 128K
描述
8-bit serial-in, parallel-out shift register

74HC164PW 数据手册

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74HC164; 74HCT164  
8-bit serial-in, parallel-out shift register  
Rev. 03 — 4 April 2005  
Product data sheet  
1. General description  
The 74HC164; 74HCT164 are high-speed Si-gate CMOS devices and are pin compatible  
with Low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC  
standard no. 7A.  
The 74HC164; 74HCT164 are 8-bit edge-triggered shift registers with serial data entry  
and an output from each of the eight stages. Data is entered serially through one of two  
inputs (DSA or DSB); either input can be used as an active HIGH enable for data entry  
through the other input. Both inputs must be connected together or an unused input must  
be tied HIGH.  
Data shifts one place to the right on each LOW-to-HIGH transition of the clock (CP) input  
and enters into Q0, which is the logical AND of the two data inputs (DSA and DSB) that  
existed one set-up time prior to the rising clock edge.  
A LOW level on the master reset (MR) input overrides all other inputs and clears the  
register asynchronously, forcing all outputs LOW.  
2. Features  
Gated serial data inputs  
Asynchronous master reset  
Complies with JEDEC standard no. 7A  
ESD protection:  
HBM EIA/JESD22-A114-B exceeds 2000 V  
MM EIA/JESD22-A115-A exceeds 200 V.  
Multiple package options  
Specified from 40 °C to +85 °C and 40 °C to +125 °C.  
3. Quick reference data  
Table 1:  
Quick reference data  
GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns.  
Symbol  
Parameter  
Conditions  
Min  
Typ  
Max  
Unit  
Type 74HC164  
tPHL, tPLH  
propagation delay  
CP to Qn  
CL = 15 pF;  
-
-
12  
11  
-
-
ns  
ns  
V
CC = 5 V  
CL = 15 pF;  
CC = 5 V  
MR to Qn  
V

74HC164PW 替代型号

型号 品牌 替代类型 描述 数据表
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