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74HC164BQ,115 PDF预览

74HC164BQ,115

更新时间: 2024-11-01 14:47:27
品牌 Logo 应用领域
恩智浦 - NXP /
页数 文件大小 规格书
20页 143K
描述
74HC(T)164 - 8-bit serial-in, parallel-out shift register QFN 14-Pin

74HC164BQ,115 技术参数

Source Url Status Check Date:2013-06-14 00:00:00是否Rohs认证: 符合
生命周期:Transferred零件包装代码:QFN
包装说明:2.50 X 3 MM, 0.85 MM HEIGHT, PLASTIC, MO-241, SOT762-1, DHVQFN-14针数:14
Reach Compliance Code:compliant风险等级:7.92
Base Number Matches:1

74HC164BQ,115 数据手册

 浏览型号74HC164BQ,115的Datasheet PDF文件第2页浏览型号74HC164BQ,115的Datasheet PDF文件第3页浏览型号74HC164BQ,115的Datasheet PDF文件第4页浏览型号74HC164BQ,115的Datasheet PDF文件第5页浏览型号74HC164BQ,115的Datasheet PDF文件第6页浏览型号74HC164BQ,115的Datasheet PDF文件第7页 
74HC164; 74HCT164  
8-bit serial-in, parallel-out shift register  
Rev. 7 — 13 June 2013  
Product data sheet  
1. General description  
The 74HC164; 74HCT164 is an 8-bit serial-in/parallel-out shift register. The device  
features two serial data inputs (DSA and DSB), eight parallel data outputs (Q0 to Q7).  
Data is entered serially through DSA or DSB and either input can be used as an active  
HIGH enable for data entry through the other input. Data is shifted on the LOW-to-HIGH  
transitions of the clock (CP) input. A LOW on the master reset input (MR) clears the  
register and forces all outputs LOW, independently of other inputs. Inputs include clamp  
diodes. This enables the use of current limiting resistors to interface inputs to voltages in  
excess of VCC  
.
2. Features and benefits  
Input levels:  
For 74HC164: CMOS level  
For 74HCT164: TTL level  
Gated serial data inputs  
Asynchronous master reset  
Complies with JEDEC standard no. 7A  
ESD protection:  
HBM JESD22-A114F exceeds 2000 V  
MM JESD22-A115-A exceeds 200 V.  
Multiple package options  
Specified from 40 C to +85 C and 40 C to +125 C.  
 
 

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