Datasheet > 74HC163PW-Q100

74HC163PW-Q100

更新时间： 2024-11-02 01:10:47

品牌	Logo	应用领域
安世 - NEXPERIA		/
页数	文件大小	规格书
19页	294K
描述
Presettable synchronous 4-bit binary counter; synchronous reset

阅读下载

中文翻译

获取价格

数据手册

如果您发现信息不准确，欢迎纠错

74HC163PW-Q100 数据手册

74HC163-Q100; 74HCT163-Q100

Presettable synchronous 4-bit binary counter; synchronous

reset

Rev. 2 — 12 October 2018

Product data sheet

1. General description

The 74HC163-Q100; 74HCT163-Q100 is a synchronous presettable binary counter with an internal

look-head carry. Synchronous operation is provided by having all flip-flops clocked simultaneously

on the positive-going edge of the clock (CP). The outputs (Q0 to Q3) of the counters may be preset

to a HIGH or LOW. A LOW at the parallel enable input (PE) disables the counting action. It causes

the data at the data inputs (D0 to D3) to be loaded into the counter on the positive-going edge of

the clock. Preset takes place regardless of the levels at count enable inputs (CEP and CET). A

LOW at the master reset input (MR) sets Q0 to Q3 LOW after the next positive-going transition

on the clock input (CP). This action occurs regardless of the levels at input pins PE, CET and

CEP. This synchronous reset feature enables the designer to modify the maximum count with

only one external NAND gate. The look-ahead carry simplifies serial cascading of the counters.

Both CEP and CET must be HIGH to count. The CET input is fed forward to enable the terminal

count output (TC). The TC output thus enabled will produce a HIGH output pulse of a duration

approximately equal to a HIGH output of Q0. This pulse can be used to enable the next cascaded

stage. Inputs include clamp diodes. This enables the use of current limiting resistors to interface

inputs to voltages in excess of V_CC

The CP to TC propagation delay and CEP to CP set-up time determine the maximum clock

frequency for the cascaded counters according to the following formula:

This product has been qualified to the Automotive Electronics Council (AEC) standard Q100

(Grade 1) and is suitable for use in automotive applications.

2. Features and benefits

•

Automotive product qualification in accordance with AEC-Q100 (Grade 1)

Specified from -40 °C to +85 °C and from -40 °C to +125 °C

•

Complies with JEDEC standard no. 7A

Input levels:

•

For 74HC163: CMOS level

For 74HCT163: TTL level

•

Synchronous counting and loading

2 count enable inputs for n-bit cascading

Synchronous reset

Positive-edge triggered clock

ESD protection:

•

MIL-STD-883, method 3015 exceeds 2000 V

HBM JESD22-A114F exceeds 2000 V

MM JESD22-A115-A exceeds 200 V (C = 200 pF; R = 0 Ω)

•

Multiple package options

12 3 4 5 6 7...19

中文翻译

下载PDF

与74HC163PW-Q100相关器件

型号	品牌	获取价格	描述	数据表
74HC163-Q100	NEXPERIA	获取价格	Presettable synchronous 4-bit binary counter; synchronous reset
74HC164	TI	获取价格	8-BIT PARALLEL-OUT SERIAL SHIFT REGISTERS
74HC164	STMICROELECTRONICS	获取价格	8 BIT SIPO SHIFT REGISTER
74HC164	NXP	获取价格	8-bit serial-in, parallel-out shift register
74HC164	ESTEK	获取价格	identical in pinout to the LS/ALS164
74HC164	SLS	获取价格	8-Bit Serial-Input/Parallel-Output8-Bit Serial-Input/Parallel-Output Shift Register
74HC164	MOTOROLA	获取价格	8-Bit Serial-Input/Parallel-Output Shift Register
74HC164	FAIRCHILD	获取价格	8-Bit Serial-in/Parallel-out Shift Register
74HC164	HITACHI	获取价格	8-bit Parallel-out Shift Register
74HC164	DIODES	获取价格	8-Bit Shift Register

与74HC163PW-Q100相关文章

英伟达新AI芯片Rubin或提前半年亮相
2024-11-05

4
苹果iPhone 17将全系采用三星/LG显示LTPO OLED面板
2024-11-05

2
三星深化印度制造布局，供应链本地化进程加速
2024-10-29

23
芯擎科技“星辰一号”自动驾驶芯片点亮成功，2025年量产在即
2024-10-29

24

产品中心

服务支持

精选活动

关于我们

帮助中心

74HC163PW-Q100

74HC163PW-Q100 数据手册

与74HC163PW-Q100相关器件

与74HC163PW-Q100相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

74HC163PW-Q100

74HC163PW-Q100 数据手册

与74HC163PW-Q100相关器件

与74HC163PW-Q100相关文章

您还可以找

您在本页遇到什么问题？