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74HC164 PDF预览

74HC164

更新时间: 2024-11-15 22:45:59
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 移位寄存器
页数 文件大小 规格书
12页 257K
描述
8 BIT SIPO SHIFT REGISTER

74HC164 数据手册

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M54HC164  
M74HC164  
8 BIT SIPO SHIFT REGISTER  
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HIGH SPEED  
PD = 15 ns (TYP.) AT VCC = 5 V  
LOW POWER DISSIPATION  
ICC = 4 µA (MAX.) AT TA = 25 °C  
OUTPUT DRIVE CAPABILITY  
10 LSTTL LOADS  
BALANCED PROPAGATION DELAYS  
tPLH = tPHL  
SYMMETRICAL OUTPUT IMPEDANCE  
IOL = IOH = 4 mA (MIN.)  
t
B1R  
(Plastic Package)  
F1R  
(Ceramic Package)  
HIGH NOISE IMMUNITY  
VNIH = VNIL = 28 % VCC (MIN.)  
WIDE OPERATING VOLTAGE RANGE  
VCC (OPR) = 2 V TO 6 V  
PIN AND FUNCTION COMPATIBLE  
WITH 54/74LS164  
M1R  
(Micro Package)  
C1R  
(Chip Carrier)  
ORDER CODES :  
M54HC164F1R  
M74HC164B1R  
M74HC164M1R  
M74HC164C1R  
PIN CONNECTIONS (top view)  
DESCRIPTION  
The M54/74HC164 is a high speed CMOS 8 BIT  
SIPO SHIFT REGISTER fabricated in silicon gate  
C2MOS technology. It has the same highspeed per-  
formance of LSTTL combined with true CMOS low  
power consumption.  
The HC164 is an 8 bit shift register with serial data  
entry and an output from each of the eight stages.  
Data is entered serially through one of two inputs (A  
or B), either of these inputs can beused asan active  
high enable for data entry through the other input.  
An unused input must be high, or both inputs con-  
nected together. Each low-to-high transition on the  
clock input shifts data one place to the right and  
entersintoQA, thelogic NAND of the twodata inputs  
(A B), the data that existed before the rising clock  
edge. A low level on the clear input overrides all  
other inputs and clearsthe register asynchronously,  
forcing all Q outputs low.  
NC =  
All inputs are equipped with protection circuits  
against static discharge and transient excess volt-  
age.  
No Internal  
Connection  
October 1992  
1/12  

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