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74HC164 PDF预览

74HC164

更新时间: 2024-11-29 22:45:59
品牌 Logo 应用领域
日立 - HITACHI 移位寄存器
页数 文件大小 规格书
9页 53K
描述
8-bit Parallel-out Shift Register

74HC164 数据手册

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HD74HC164  
8-bit Parallel-out Shift Register  
Description  
This 8-bit shift register has gated serial inputs and clear. Each register bit is a D-type master/slave flip-  
flop. Inputs A & B permit complete control over the incoming data. A low at either or both inputs inhibits  
entry of new data and resets the first flip-vlop to the low level at the next clock pulse. A high level on the  
input enables the other input which will then determine the state of the first flip-flop. Data at the serial  
inputs may be changed while the clock is high or low, but only information meeting the setup and hold time  
requirements will be entered. Data is serially shifted in and out of the 8-bit register during the positive  
going transition of the clock pulse. Clear is independent of the clock and accomplished by a low level at  
the clear input.  
Features  
High Speed Operation: tpd (Clock to Q) = 14.5 ns typ (CL = 50 pF)  
High Output Current: Fanout of 10 LSTTL Loads  
Wide Operating Voltage: VCC = 2 to 6 V  
Low Input Current: 1 µA max  
Low Quiescent Supply Current: ICC (static) = 4 µA max  
Function Table  
Inputs  
Outputs  
Clear  
Clock  
A
X
X
L
B
X
X
X
L
QA  
L
QB  
L
·········  
·········  
·········  
·········  
·········  
·········  
QH  
L
L
X
H
H
H
H
QAo  
L
QBo  
QAn  
QAn  
QAn  
QHo  
QGn  
QGn  
QGn  
X
H
L
H
H
QAo to QHo = Outputs remain unchanged.  
An to QGn = Data shifted from the previous stage on a positive edge at the clock input.  
Q

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