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74HC132D PDF预览

74HC132D

更新时间: 2024-09-13 20:19:55
品牌 Logo 应用领域
东芝 - TOSHIBA 光电二极管逻辑集成电路触发器
页数 文件大小 规格书
7页 158K
描述
NAND GATE

74HC132D 技术参数

是否Rohs认证: 符合生命周期:Active
包装说明:SOP,Reach Compliance Code:unknown
HTS代码:8542.39.00.01Factory Lead Time:12 weeks
风险等级:1.56系列:HC/UH
JESD-30 代码:R-PDSO-G14长度:8.65 mm
逻辑集成电路类型:NAND GATE功能数量:4
输入次数:2端子数量:14
最高工作温度:85 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
峰值回流温度(摄氏度):NOT SPECIFIED传播延迟(tpd):140 ns
座面最大高度:1.75 mm最大供电电压 (Vsup):6 V
最小供电电压 (Vsup):2 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:3.9 mm
Base Number Matches:1

74HC132D 数据手册

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74HC132D  
CMOS Digital Integrated Circuits Silicon Monolithic  
74HC132D  
1. Functional Description  
Quad 2-Input Schmitt NAND Gate  
2. General  
The 74HC132D is a high speed CMOS 2-INPUT NAND SCHMITT TRIGGER GATE fabricated with silicon gate  
C2MOS technology.  
It achieves the high speed operation similar to equivalent LSTTL while maintaining the CMOS low power  
dissipation.  
Pin configuration and function are the same as the 74HC00D but the inputs have 25% VCC hysteresis and with  
its schmitt trigger inputs, the 74HC132D can be used as a line receiver for slow input signals.  
All inputs are equipped with protection circuits against static discharge or transient excess voltage.  
3. Features  
(1) High speed: tpd = 11 ns (typ.) at VCC = 5 V  
(2) Low power dissipation: ICC = 1.0 µA (max) at Ta = 25  
(3) High noise immunity: VH = 1.1 V (typ.) at VCC = 4.5 V  
(4) Balanced propagation delays: tPLH tPHL  
(5) Wide operating voltage range: VCC(opr) = 2.0 to 6.0 V  
4. Packaging  
SOIC14  
Start of commercial production  
2016-04  
©2016 Toshiba Corporation  
2016-05-25  
Rev.2.0  
1

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