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74HC132DR2G PDF预览

74HC132DR2G

更新时间: 2024-09-13 08:03:39
品牌 Logo 应用领域
安森美 - ONSEMI 触发器
页数 文件大小 规格书
9页 135K
描述
Quad 2−Input NAND Gate with Schmitt−Trigger Inputs High−Performance Silicon−Gate CMOS

74HC132DR2G 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:SOIC包装说明:SOP, SOP14,.25
针数:14Reach Compliance Code:unknown
HTS代码:8542.39.00.01Factory Lead Time:1 week
风险等级:7.04系列:HC/UH
JESD-30 代码:R-PDSO-G14JESD-609代码:e3
长度:8.65 mm负载电容(CL):50 pF
逻辑集成电路类型:NAND GATE最大I(ol):0.004 A
湿度敏感等级:1功能数量:4
输入次数:2端子数量:14
最高工作温度:125 °C最低工作温度:-55 °C
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装等效代码:SOP14,.25封装形状:RECTANGULAR
封装形式:SMALL OUTLINE包装方法:TAPE AND REEL
峰值回流温度(摄氏度):260电源:2/6 V
Prop。Delay @ Nom-Sup:38 ns传播延迟(tpd):190 ns
认证状态:Not Qualified施密特触发器:YES
座面最大高度:1.75 mm子类别:Gates
最大供电电压 (Vsup):6 V最小供电电压 (Vsup):2 V
标称供电电压 (Vsup):4.5 V表面贴装:YES
技术:CMOS温度等级:MILITARY
端子面层:Tin (Sn)端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
处于峰值回流温度下的最长时间:40宽度:3.9 mm

74HC132DR2G 数据手册

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74HC132  
Quad 2−Input NAND Gate  
with Schmitt−Trigger Inputs  
HighPerformance SiliconGate CMOS  
The 74HC132 is identical in pinout to the LS132. The device inputs  
are compatible with standard CMOS outputs; with pullup resistors,  
they are compatible with LSTTL outputs.  
http://onsemi.com  
The HC132 can be used to enhance noise immunity or to square up  
slowly changing waveforms.  
MARKING  
DIAGRAMS  
Features  
14  
Output Drive Capability: 10 LSTTL Loads  
Outputs Directly Interface to CMOS, NMOS, and TTL  
Operating Voltage Range: 2.0 to 6.0 V  
Low Input Current: 1.0 mA  
SOIC14  
D SUFFIX  
CASE 751A  
HC132G  
AWLYWW  
1
High Noise Immunity Characteristic of CMOS Devices  
In Compliance with the Requirements as Defined by JEDEC  
Standard No. 7A  
ESD Performance: HBM > 2000 V; Machine Model > 200 V  
Chip Complexity: 72 FETs or 18 Equivalent Gates  
These are PbFree Devices  
14  
1
HC  
132  
TSSOP14  
DT SUFFIX  
CASE 948G  
ALYW G  
G
HC132 = Device Code  
A
= Assembly Location  
L, WL = Wafer Lot  
= Year  
A1  
B1  
1
2
14  
13 B4  
12  
V
CC  
Y
W, WW = Work Week  
Y1  
A2  
3
4
A4  
G or G = PbFree Package  
11 Y4  
10 B3  
(Note: Microdot may be in either location)  
B2  
Y2  
5
6
9
8
A3  
Y3  
GND  
7
FUNCTION TABLE  
Inputs  
Output  
Y
Figure 1. Pin Assignment  
A
B
L
L
H
H
L
H
L
H
H
H
L
H
ORDERING INFORMATION  
See detailed ordering and shipping information in the package  
dimensions section on page 2 of this data sheet.  
©
Semiconductor Components Industries, LLC, 2007  
1
Publication Order Number:  
March, 2007 Rev. 1  
74HC132/D  

74HC132DR2G 替代型号

型号 品牌 替代类型 描述 数据表
MC74HC00ADR2G ONSEMI

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