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74F1071

更新时间: 2024-11-28 22:15:59
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD /
页数 文件大小 规格书
6页 95K
描述
18-Bit Undershoot/Overshoot Clamp

74F1071 数据手册

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October 1994  
Revised August 1999  
74F1071  
18-Bit Undershoot/Overshoot Clamp  
and ESD Protection Device  
General Description  
Features  
The 74F1071 is an 18-bit undershoot/overshoot clamp  
which is designed to limit bus voltages and also to protect  
more sensitive devices from electrical overstress due to  
electrostatic discharge (ESD). The inputs of the device  
aggressively clamp voltage excursions nominally at 0.5V  
below and 7V above ground.  
18-bit array structure in 20-pin package  
FAST Bipolar voltage clamping action  
Dual center pin grounds for min inductance  
Robust design for ESD protection  
Low input capacitance  
Optimum voltage clamping for 5V CMOS/TTL  
applications  
Ordering Code:  
Order Number Package Number  
Package Description  
74F1071SC  
74F1071MSA  
74F1071MTC  
M20B  
MSA20  
MTC20  
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide  
20-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide  
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide  
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.  
Connection Diagram  
Note: Simplified Component Representation  
FAST is a registered trademark of Fairchild Semiconductor Corporation.  
© 1999 Fairchild Semiconductor Corporation  
DS011685  
www.fairchildsemi.com  

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