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74F109PC PDF预览

74F109PC

更新时间: 2024-11-28 22:37:03
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 触发器逻辑集成电路光电二极管
页数 文件大小 规格书
7页 82K
描述
Dual JK Positive Edge-Triggered Flip-Flop

74F109PC 数据手册

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April 1988  
Revised November 1999  
74F109  
Dual JK Positive Edge-Triggered Flip-Flop  
Asynchronous Inputs:  
General Description  
LOW input to SD sets Q to HIGH level  
LOW input to CD sets Q to LOW level  
The F109 consists of two high-speed, completely indepen-  
dent transition clocked JK flip-flops. The clocking operation  
is independent of rise and fall times of the clock waveform.  
The JK design allows operation as a D-type flip-flop (refer  
to F74 data sheet) by connecting the J and K inputs.  
Clear and Set are independent of clock  
Simultaneous LOW on CD and SD makes  
both Q and Q HIGH  
Ordering Code:  
Order Number Package Number  
Package Description  
74F109SC  
74F109SJ  
74F109PC  
M16A  
M16D  
N16E  
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150Narrow Body  
16-Lead Small Outline Package (SOP), EIAJ TYPE 11, 5.3mm Wide  
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300Wide  
Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.  
Logic Symbols  
Connection Diagram  
IEEE/IEC  
© 1999 Fairchild Semiconductor Corporation  
DS009471  
www.fairchildsemi.com  

74F109PC 替代型号

型号 品牌 替代类型 描述 数据表
SN74F109N TI

功能相似

DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET
74F109SC FAIRCHILD

功能相似

Dual JK Positive Edge-Triggered Flip-Flop

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74F109SCX TI

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