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74F109SCQR PDF预览

74F109SCQR

更新时间: 2024-01-17 09:07:55
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 触发器
页数 文件大小 规格书
7页 81K
描述
J-Kbar Flip-Flop, F/FAST Series, 2-Func, Positive Edge Triggered, 2-Bit, Complementary Output, TTL, PDSO16, 0.150 INCH, SOIC-16

74F109SCQR 技术参数

生命周期:Obsolete零件包装代码:SOIC
包装说明:SOP,针数:16
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.11系列:F/FAST
JESD-30 代码:R-PDSO-G16长度:9.9 mm
逻辑集成电路类型:J-KBAR FLIP-FLOP位数:2
功能数量:2端子数量:16
最高工作温度:70 °C最低工作温度:
输出极性:COMPLEMENTARY封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装形状:RECTANGULAR
封装形式:SMALL OUTLINE传播延迟(tpd):9.2 ns
认证状态:Not Qualified座面最大高度:1.75 mm
最大供电电压 (Vsup):5.25 V最小供电电压 (Vsup):4.75 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:TTL温度等级:COMMERCIAL
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL触发器类型:POSITIVE EDGE
宽度:3.9 mm最小 fmax:125 MHz
Base Number Matches:1

74F109SCQR 数据手册

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April 1988  
Revised September 2000  
74F109  
Dual JK Positive Edge-Triggered Flip-Flop  
Asynchronous Inputs:  
General Description  
LOW input to SD sets Q to HIGH level  
LOW input to CD sets Q to LOW level  
The F109 consists of two high-speed, completely indepen-  
dent transition clocked JK flip-flops. The clocking operation  
is independent of rise and fall times of the clock waveform.  
The JK design allows operation as a D-type flip-flop (refer  
to F74 data sheet) by connecting the J and K inputs.  
Clear and Set are independent of clock  
Simultaneous LOW on CD and SD makes  
both Q and Q HIGH  
Ordering Code:  
Order Number Package Number  
Package Description  
74F109SC  
74F109SJ  
74F109PC  
M16A  
M16D  
N16E  
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow  
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide  
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide  
Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.  
Logic Symbols  
Connection Diagram  
IEEE/IEC  
© 2000 Fairchild Semiconductor Corporation  
DS009471  
www.fairchildsemi.com  

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