Datasheet > 74F109_00

74F109_00

更新时间： 2025-09-18 04:28:47

品牌	Logo	应用领域
飞兆/仙童 - FAIRCHILD		触发器
页数	文件大小	规格书
7页	81K
描述
Dual JK Positive Edge-Triggered Flip-Flop

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74F109_00 数据手册

April 1988

Revised September 2000

74F109

Dual JK Positive Edge-Triggered Flip-Flop

Asynchronous Inputs:

General Description

LOW input to S_Dsets Q to HIGH level

LOW input to C_Dsets Q to LOW level

The F109 consists of two high-speed, completely indepen-

dent transition clocked JK flip-flops. The clocking operation

is independent of rise and fall times of the clock waveform.

The JK design allows operation as a D-type flip-flop (refer

to F74 data sheet) by connecting the J and K inputs.

Clear and Set are independent of clock

Simultaneous LOW on C_Dand S_Dmakes

both Q and Q HIGH

Ordering Code:

Order Number Package Number

Package Description

74F109SC

74F109SJ

74F109PC

M16A

M16D

N16E

16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow

16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.

Logic Symbols

Connection Diagram

IEEE/IEC

DS009471

www.fairchildsemi.com

12 3 4 5 6 7

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型号	品牌	获取价格	描述	数据表
74F10D	YAGEO	获取价格	NAND Gate, F/FAST Series, 3-Func, 3-Input, TTL, PDSO14
74F10D-T	YAGEO	获取价格	NAND Gate, F/FAST Series, 3-Func, 3-Input, TTL, PDSO14
74F10DC	FAIRCHILD	获取价格	NAND Gate, F/FAST Series, 3-Func, 3-Input, TTL, CDIP14, CERAMIC, DIP-14
74F10DCQM	FAIRCHILD	获取价格	NAND Gate, TTL, CDIP14,
74F10DCQR	FAIRCHILD	获取价格	暂无描述
74F10L1C	FAIRCHILD	获取价格	NAND Gate, F/FAST Series, 3-Func, 3-Input, TTL, CQCC20, CERAMIC, LCC-20
74F10L1CQR	FAIRCHILD	获取价格	NAND Gate, F/FAST Series, 3-Func, 3-Input, TTL, CQCC20, CERAMIC, LCC-20
74F10N	YAGEO	获取价格	NAND Gate, F/FAST Series, 3-Func, 3-Input, TTL, PDIP14
74F10PC	FAIRCHILD	获取价格	Triple 3-Input NAND Gate
74F10PC	NSC	获取价格	Triple 3-Input NAND Gate