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74F10SJCX PDF预览

74F10SJCX

更新时间: 2024-11-29 13:04:55
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD
页数 文件大小 规格书
4页 51K
描述
NAND Gate, F/FAST Series, 3-Func, 3-Input, TTL, PDSO14, 0.300 INCH, EIAJ, PLASTIC, SOP-14

74F10SJCX 技术参数

生命周期:Obsolete零件包装代码:SOIC
包装说明:SOP,针数:14
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.44系列:F/FAST
JESD-30 代码:R-PDSO-G14长度:10.1 mm
逻辑集成电路类型:NAND GATE功能数量:3
输入次数:3端子数量:14
最高工作温度:70 °C最低工作温度:
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
传播延迟(tpd):5.3 ns认证状态:Not Qualified
座面最大高度:2.1 mm最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:TTL
温度等级:COMMERCIAL端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
宽度:5.3 mmBase Number Matches:1

74F10SJCX 数据手册

 浏览型号74F10SJCX的Datasheet PDF文件第2页浏览型号74F10SJCX的Datasheet PDF文件第3页浏览型号74F10SJCX的Datasheet PDF文件第4页 
April 1988  
Revised July 1999  
74F10  
Triple 3-Input NAND Gate  
General Description  
This device contains three independent gates, each of  
which performs the logic NAND function.  
Ordering Code:  
Order Number Package Number  
Package Description  
74F10SC  
74F10SJ  
74F10PC  
M14A  
M14D  
N14A  
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow  
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide  
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide  
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.  
Logic Symbol  
Connection Diagram  
IEEE/IEC  
Unit Loading/Fan Out  
Input IIH/IIL  
U.L.  
Pin Names  
Description  
Output IOH/IOL  
HIGH/LOW  
1.0/1.0  
An, Bn, Cn  
On  
Inputs  
20 µA/0.6 mA  
1 mA/20 mA  
Outputs  
50/33.3  
© 1999 Fairchild Semiconductor Corporation  
DS009458  
www.fairchildsemi.com  

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