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74F109PC PDF预览

74F109PC

更新时间: 2024-11-28 22:37:03
品牌 Logo 应用领域
美国国家半导体 - NSC 触发器逻辑集成电路光电二极管
页数 文件大小 规格书
10页 136K
描述
Dual JK Positive Edge-Triggered Flip-Flop

74F109PC 数据手册

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November 1994  
54F/74F109  
Dual JK Positive Edge-Triggered Flip-Flop  
LOW input to CD sets Q to LOW level  
General Description  
Clear and Set are independent of clock  
The ’F109 consists of two high-speed, completely indepen-  
dent transition clocked JK flip-flops. The clocking operation  
is independent of rise and fall times of the clock waveform.  
The JK design allows operation as a D flip-flop (refer to ’F74  
data sheet) by connecting the J and K inputs.  
Simultaneous LOW on CD and SD makes both Q and Q  
HIGH  
Features  
n Guaranteed 4000V minimum ESD protection.  
Asynchronous Inputs:  
LOW input to SD sets Q to HIGH level  
Ordering Code: See Section 0  
DSXXX  
Commercial  
Military  
Package  
Number  
N16E  
Package Description  
74F109PC  
16-Lead (0.300" Wide) Molded Dual-in-Line  
16-Lead Ceramic Dual-in-Line  
54F109DM (Note 2)  
J16A  
74F109SC (Note 1)  
74F109SJ (Note 1)  
M16A  
16-Lead (0.150" Wide) Molded Small Outline,  
JEDEC  
M16D  
16-Lead (0.300" Wide) Molded Small Outline,  
EIAJ  
54F109FM (Note 2)  
54F109LM (Note 2)  
W16A  
E20A  
16-Lead Cerpack  
16-Lead Ceramic Leadless Chip Carrier, Type C  
=
Note 1: Devices also available in 13" reel. Use suffix SCX and SJX.  
=
Note 2: Military grade device with environmental and burn-in processing. Use suffix DMQB, FMQB and LMQB.  
Logic Symbols  
IEEE/IEC  
DS009471-3  
DS009471-4  
DS009471-6  
FAST® and TRI-STATE® are registered trademarks of National Semiconductor Corporation.  
© 1997 National Semiconductor Corporation  
DS009471  
www.national.com  
1
PrintDate=1997/08/28 PrintTime=11:45:22 10182 ds009471 Rev. No. 1 cmserv Proof  
1

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