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74AVCH1T45GM,115 PDF预览

74AVCH1T45GM,115

更新时间: 2024-11-09 21:18:03
品牌 Logo 应用领域
恩智浦 - NXP /
页数 文件大小 规格书
22页 103K
描述
74AVCH1T45 - Dual-supply voltage level translator/transceiver; 3-state SON 6-Pin

74AVCH1T45GM,115 技术参数

是否Rohs认证: 符合生命周期:Transferred
零件包装代码:SON包装说明:1 X 1.45 MM, 0.50 MM HEIGHT, PLASTIC, MO-252, SOT-886, XSON-6
针数:6Reach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:5.29
控制类型:COMMON CONTROL计数方向:BIDIRECTIONAL
系列:AVCJESD-30 代码:R-PDSO-N6
JESD-609代码:e3长度:1.45 mm
逻辑集成电路类型:BUS TRANSCEIVER最大I(ol):0.006 A
湿度敏感等级:1位数:1
功能数量:1端口数量:2
端子数量:6最高工作温度:125 °C
最低工作温度:-40 °C输出特性:3-STATE
输出极性:TRUE封装主体材料:PLASTIC/EPOXY
封装代码:VSON封装等效代码:SOLCC6,.04,20
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, VERY THIN PROFILE
包装方法:TAPE AND REEL峰值回流温度(摄氏度):260
电源:1.2/3.3 VProp。Delay @ Nom-Sup:9.9 ns
传播延迟(tpd):9.9 ns认证状态:Not Qualified
座面最大高度:0.5 mm子类别:Bus Driver/Transceivers
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):0.8 V
标称供电电压 (Vsup):1.1 V表面贴装:YES
技术:CMOS温度等级:AUTOMOTIVE
端子面层:Tin (Sn)端子形式:NO LEAD
端子节距:0.5 mm端子位置:DUAL
处于峰值回流温度下的最长时间:30翻译:1.5/3.3V &1.5/3.3V
宽度:1 mmBase Number Matches:1

74AVCH1T45GM,115 数据手册

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74AVCH1T45  
Dual supply translating transceiver; 3-state  
Rev. 02 — 5 May 2009  
Product data sheet  
1. General description  
The 74AVCH1T45 is a single bit, dual supply transceiver that enables bidirectional level  
translation. It features two data input-output ports (A and B), a direction control input (DIR)  
and dual supply pins (VCC(A) and VCC(B)). Both VCC(A) and VCC(B) can be supplied at any  
voltage between 0.8 V and 3.6 V making the device suitable for translating between any of  
the low voltage nodes (0.8 V, 1.2 V, 1.5 V, 1.8 V, 2.5 V and 3.3 V). Pins A and DIR are  
referenced to VCC(A) and pin B is referenced to VCC(B). A HIGH on DIR allows transmission  
from A to B and a LOW on DIR allows transmission from B to A.  
The device is fully specified for partial power-down applications using IOFF. The IOFF  
circuitry disables the output, preventing any damaging backflow current through the  
device when it is powered down. In suspend mode when either VCC(A) or VCC(B) are at  
GND level, both A and B are in the high-impedance OFF-state.  
The 74AVCH1T45 has active bus hold circuitry which is provided to hold unused or  
floating data inputs at a valid logic level. This feature eliminates the need for external  
pull-up or pull-down resistors.  
2. Features  
I Wide supply voltage range:  
N VCC(A): 0.8 V to 3.6 V  
N VCC(B): 0.8 V to 3.6 V  
I High noise immunity  
I Complies with JEDEC standards:  
N JESD8-12 (0.8 V to 1.3 V)  
N JESD8-11 (0.9 V to 1.65 V)  
N JESD8-7 (1.2 V to 1.95 V)  
N JESD8-5 (1.8 V to 2.7 V)  
N JESD8-B (2.7 V to 3.6 V)  
I ESD protection:  
N HBM JESD22-A114E Class 3B exceeds 8000 V  
N MM JESD22-A115-A exceeds 200 V  
N CDM JESD22-C101C exceeds 1000 V  
I Maximum data rates:  
N 500 Mbit/s (1.8 V to 3.3 V translation)  
N 320 Mbit/s (< 1.8 V to 3.3 V translation)  
N 320 Mbit/s (translate to 2.5 V or 1.8 V)  
N 280 Mbit/s (translate to 1.5 V)  
 
 

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