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74AVCH2T45DCTTE4

更新时间： 2024-09-16 06:31:51
品牌 Logo 应用领域
德州仪器 - TI 总线驱动器总线收发器逻辑集成电路光电二极管输出元件
页数 文件大小 规格书
24页 640K
描述
DUAL-BIT DUAL-SUPPLY BUS TRANSCEIVER WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS

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中文翻译

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74AVCH2T45DCTTE4 技术参数

是否无铅：不含铅是否Rohs认证：符合
生命周期：Active零件包装代码：SOIC
包装说明：SSOP-8针数：8
Reach Compliance Code：compliantHTS代码：8542.39.00.01
Factory Lead Time：6 weeks风险等级：5.24
Is Samacsys：N其他特性：TWO SEPARATE CONFIGURABLE POWER SUPPLY RAILS FOR PORT A AND PORT B
控制类型：COMMON CONTROL计数方向：BIDIRECTIONAL
系列：AVCJESD-30 代码：R-PDSO-G8
JESD-609代码：e4长度：2.95 mm
逻辑集成电路类型：BUS TRANSCEIVER最大I（ol）：0.012 A
湿度敏感等级：1位数：2
功能数量：1端口数量：2
端子数量：8最高工作温度：85 °C
最低工作温度：-40 °C输出特性：3-STATE
输出极性：TRUE封装主体材料：PLASTIC/EPOXY
封装代码：LSSOP封装等效代码：SSOP8,.16
封装形状：RECTANGULAR封装形式：SMALL OUTLINE, LOW PROFILE, SHRINK PITCH
包装方法：TR峰值回流温度（摄氏度）：260
电源：1.5/3.3 V最大电源电流（ICC）：0.02 mA
Prop。Delay @ Nom-Sup：5.4 ns传播延迟（tpd）：5.4 ns
认证状态：Not Qualified座面最大高度：1.3 mm
子类别：Bus Driver/Transceiver最大供电电压 (Vsup)：3.6 V
最小供电电压 (Vsup)：1.2 V标称供电电压 (Vsup)：1.5 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式：GULL WING端子节距：0.65 mm
端子位置：DUAL处于峰值回流温度下的最长时间：NOT SPECIFIED
翻译：1.5/3.3V &1.5/3.3V宽度：2.8 mm
Base Number Matches：1

74AVCH2T45DCTTE4 数据手册

 浏览型号74AVCH2T45DCTTE4的Datasheet PDF文件第2页浏览型号74AVCH2T45DCTTE4的Datasheet PDF文件第3页浏览型号74AVCH2T45DCTTE4的Datasheet PDF文件第4页浏览型号74AVCH2T45DCTTE4的Datasheet PDF文件第5页浏览型号74AVCH2T45DCTTE4的Datasheet PDF文件第6页浏览型号74AVCH2T45DCTTE4的Datasheet PDF文件第7页 
SN74AVCH2T45  
DUAL-BIT DUAL-SUPPLY BUS TRANSCEIVER  
WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS  
www.ti.com  
SCES582F–JULY 2004–REVISED NOVEMBER 2007  
1
FEATURES  
2
•
Available in the Texas Instruments NanoFree™  
DCT OR DCU PACKAGE  
(TOP VIEW)  
Package  
•
•
Control Inputs VIH/VIL Levels Are Referenced to  
VCCA Voltage  
VCCA  
A1  
A2  
GND  
VCCB  
B1  
B2  
1
2
3
4
8
7
6
5
Fully Configurable Dual-Rail Design Allows  
Each Port to Operate Over the Full 1.2-V to  
3.6-V Power-Supply Range  
DIR  
•
•
I/Os Are 4.6-V Tolerant  
Ioff Supports Partial Power-Down-Mode  
Operation  
YZP PACKAGE  
(BOTTOM VIEW)  
•
•
Bus Hold on Data Inputs Eliminates the Need  
for External Pullup/Pulldown Resistors  
D1  
C1  
D2  
C2  
4
3
2
1
5
6
7
8
GND  
A2  
DIR  
B2  
Max Data Rates  
–
–
–
–
–
500 Mbps (1.8-V to 3.3-V Translation)  
320 Mbps (<1.8-V to 3.3-V Translation)  
320 Mbps (Translate to 2.5 V or 1.8 V)  
280 Mbps (Translate to 1.5 V)  
B1  
A1  
B2  
A2  
A1  
B1  
VCCA  
VCCB  
240 Mbps (Translate to 1.2 V)  
•
•
Latch-Up Performance Exceeds 100 mA Per  
JESD 78, Class II  
ESD Protection Exceeds JESD 22  
–
–
–
2000-V Human-Body Model (A114-A)  
200-V Machine Model (A115-A)  
1000-V Charged-Device Model (C101)  
DESCRIPTION/ORDERING INFORMATION  
This dual-bit noninverting bus transceiver uses two separate configurable power-supply rails. The  
SN74AVCH2T45 is optimized to operate with VCCA/VCCB set at 1.4 V to 3.6 V. It is operational with VCCA/VCCB as  
low as 1.2 V. The A port is designed to track VCCA. VCCA accepts any supply voltage from 1.2 V to 3.6 V. The B  
port is designed to track VCCB. VCCB accepts any supply voltage from 1.2 V to 3.6 V. This allows for universal  
low-voltage bidirectional translation between any of the 1.2-V, 1.5-V, 1.8-V, 2.5-V, and 3.3-V voltage nodes.  
ORDERING INFORMATION  
TA  
PACKAGE(1)(2)  
ORDERABLE PART NUMBER  
TOP-SIDE MARKING(3)  
NanoFree™ – WCSP (DSBGA)  
0.23-mm Large Bump – YZP (Pb-free)  
Reel of 3000  
SN74AVCH2T45YZPR  
_ _ _TF_  
–40°C to 85°C  
SSOP – DCT  
Reel of 3000  
Reel of 3000  
SN74AVCH2T45DCTR  
SN74AVCH2T45DCUR  
ET2_ _ _  
ET2_  
VSSOP – DCU  
(1) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.  
(2) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI  
website at www.ti.com.  
(3) DCT: The actual top-side marking has three additional characters that designate the year, month, and assembly/test site.  
DCU: The actual top-side marking has one additional character that designates the assembly/test site.  
YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following  
character to designate the assembly/test site. Pin 1 identifier indicates solder-bump composition (1 = SnPb, • = Pb-free).  
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
2
NanoFree is a trademark of Texas Instruments.  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
Copyright © 2004–2007, Texas Instruments Incorporated  
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中文翻译

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74AVCH2T45DCTTE4 替代型号

型号 品牌 替代类型 描述 数据表
SN74AVCH2T45DCTT TI

类似代替

 DUAL-BIT DUAL-SUPPLY BUS TRANSCEIVER WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUT
SN74AVCH2T45DCTR TI

类似代替

 DUAL-BIT DUAL-SUPPLY BUS TRANSCEIVER WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUT

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