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74AVCH20T245DGG PDF预览

74AVCH20T245DGG

更新时间： 2024-11-23 20:05:23
品牌 Logo 应用领域
恩智浦 - NXP 光电二极管输出元件逻辑集成电路
页数 文件大小 规格书
28页 248K
描述
AVC SERIES, DUAL 10-BIT TRANSCEIVER, TRUE OUTPUT, PDSO56, 6.10 MM, PLASTIC, MO-153, SOT364-1, TSSOP-56

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74AVCH20T245DGG 技术参数

是否Rohs认证： 符合生命周期：Transferred
零件包装代码：TSSOP包装说明：6.10 MM, PLASTIC, MO-153, SOT364-1, TSSOP-56
针数：56Reach Compliance Code：unknown
HTS代码：8542.39.00.01风险等级：5.68
系列：AVCJESD-30 代码：R-PDSO-G56
长度：14 mm逻辑集成电路类型：BUS TRANSCEIVER
湿度敏感等级：1位数：10
功能数量：2端口数量：2
端子数量：56最高工作温度：125 °C
最低工作温度：-40 °C输出特性：3-STATE
输出极性：TRUE封装主体材料：PLASTIC/EPOXY
封装代码：TSSOP封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH峰值回流温度（摄氏度）：260
传播延迟（tpd）：10.4 ns认证状态：Not Qualified
座面最大高度：1.2 mm最大供电电压 (Vsup)：3.6 V
最小供电电压 (Vsup)：0.8 V标称供电电压 (Vsup)：1.1 V
表面贴装：YES技术：CMOS
温度等级：AUTOMOTIVE端子形式：GULL WING
端子节距：0.5 mm端子位置：DUAL
处于峰值回流温度下的最长时间：30宽度：6.1 mm
Base Number Matches：1

74AVCH20T245DGG 数据手册

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74AVCH20T245  
20-bit dual supply translating transceiver with configurable  
voltage translation; 3-state  
Rev. 4 — 14 December 2011  
Product data sheet  
1. General description  
The 74AVCH20T245 is a 20-bit, dual supply transceiver that enables bi-directional voltage  
level translation. The device can be used as two 10-bit transceivers or as a single 20-bit  
transceiver. It features four 10-bit input-output ports (1An, 1Bn and 2An, 2Bn), two output  
enable inputs (nOE), two direction inputs (nDIR) and dual supplies (VCC(A) and VCC(B)).  
V
CC(A) and VCC(B) can be independently supplied at any voltage between 0.8 V and 3.6 V  
making the device suitable for bi-directional voltage level translation between any of the  
low voltage nodes: 0.8 V, 1.2 V, 1.5 V, 1.8 V, 2.5 V and 3.3 V. The 1An and 2An ports, nOE  
and nDIR are referenced to VCC(A), the 1Bn and 2Bn ports are referenced to VCC(B). A  
HIGH on a 1DIR allows transmission from 1An to 1Bn and a LOW on 1DIR allows  
transmission from 1Bn to 1An. A HIGH on nOE causes the outputs to assume a HIGH  
impedance OFF-state.  
The device is fully specified for partial power-down applications using IOFF. The IOFF  
circuitry disables the output, preventing any damaging backflow current through the  
device when it is powered down. In suspend mode when either VCC(A) or VCC(B) are at  
GND level, all output ports will assume a high impedance OFF-state. The bus hold  
circuitry on the powered-up side always stays active.  
2. Features and benefits  
Wide supply voltage range:  
VCC(A): 0.8 V to 3.6 V  
VCC(B): 0.8 V to 3.6 V  
Complies with JEDEC standards:  
JESD8-12 (0.8 V to 1.3 V)  
JESD8-11 (0.9 V to 1.65 V)  
JESD8-7 (1.2 V to 1.95 V)  
JESD8-5 (1.8 V to 2.7 V)  
JESD8-B (2.7 V to 3.6 V)  
ESD protection:  
HBM JESD22-A114E Class 3B exceeds 8000 V  
MM JESD22-A115-A exceeds 200 V  
CDM JESD22-C101C exceeds 1000 V  
Maximum data rates:  
380 Mbit/s (1.8 V to 3.3 V translation)  
260 Mbit/s (1.1 V to 3.3 V translation)  
260 Mbit/s (1.1 V to 2.5 V translation)  
 
 
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