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74AVCH1T45GW PDF预览

74AVCH1T45GW

更新时间: 2024-11-07 11:12:35
品牌 Logo 应用领域
安世 - NEXPERIA 光电二极管逻辑集成电路
页数 文件大小 规格书
22页 310K
描述
Dual-supply voltage level translator/transceiver; 3-stateProduction

74AVCH1T45GW 技术参数

是否Rohs认证: 符合生命周期:Active
包装说明:TSSOP,Reach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:5.27
系列:AVCJESD-30 代码:R-PDSO-G6
JESD-609代码:e3长度:2 mm
逻辑集成电路类型:BUS TRANSCEIVER湿度敏感等级:1
位数:1功能数量:1
端口数量:2端子数量:6
最高工作温度:125 °C最低工作温度:-40 °C
输出特性:3-STATE输出极性:TRUE
封装主体材料:PLASTIC/EPOXY封装代码:TSSOP
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度(摄氏度):260传播延迟(tpd):9.9 ns
座面最大高度:1.1 mm最大供电电压 (Vsup):3.6 V
最小供电电压 (Vsup):0.8 V标称供电电压 (Vsup):1.1 V
表面贴装:YES技术:CMOS
温度等级:AUTOMOTIVE端子面层:Tin (Sn)
端子形式:GULL WING端子节距:0.65 mm
端子位置:DUAL处于峰值回流温度下的最长时间:30
宽度:1.25 mm

74AVCH1T45GW 数据手册

 浏览型号74AVCH1T45GW的Datasheet PDF文件第2页浏览型号74AVCH1T45GW的Datasheet PDF文件第3页浏览型号74AVCH1T45GW的Datasheet PDF文件第4页浏览型号74AVCH1T45GW的Datasheet PDF文件第5页浏览型号74AVCH1T45GW的Datasheet PDF文件第6页浏览型号74AVCH1T45GW的Datasheet PDF文件第7页 
74AVCH1T45  
Dual-supply voltage level translator/transceiver; 3-state  
Rev. 6.1 — 31 March 2022  
Product data sheet  
1. General description  
The 74AVCH1T45 is a single bit, dual supply transceiver that enables bidirectional level translation.  
The 74AVCH1T45 has active bus hold circuitry which is provided to hold unused or floating data  
inputs at a valid logic level. This feature eliminates the need for external pull-up or pull-down  
resistors.The device is fully specified for partial power-down applications using IOFF. The IOFF  
circuitry disables the output, preventing potentially damaging backflow current through the device  
when it is powered down.  
2. Features and benefits  
Wide supply voltage range from 0.8 V to 3.6 V  
High noise immunity  
CMOS low power dissipation  
Overvoltage tolerant inputs to 3.6 V  
Dynamically controlled outpus  
Complies with JEDEC standards:  
JESD8-12 (0.8 V to 1.3 V)  
JESD8-11 (0.9 V to 1.65 V)  
JESD8-7 (1.65 V to 1.95 V)  
JESD8-5 (2.3 V to 2.7 V)  
JESD8C (2.7 V to 3.6 V)  
ESD protection:  
HBM JESD22-A114E Class 3B exceeds 8000 V  
MM JESD22-A115-A exceeds 200 V  
CDM JESD22-C101C exceeds 1000 V  
Maximum data rates:  
500 Mbit/s (1.8 V to 3.3 V translation)  
320 Mbit/s (< 1.8 V to 3.3 V translation)  
320 Mbit/s (translate to 2.5 V or 1.8 V)  
280 Mbit/s (translate to 1.5 V)  
240 Mbit/s (translate to 1.2 V)  
Suspend mode  
Bus hold on data inputs  
Latch-up performance exceeds 100 mA per JESD 78 Class II  
Low noise overshoot and undershoot < 10 % of VCC  
IOFF circuitry provides partial Power-down mode operation  
Multiple package options  
Specified from -40 °C to +85 °C and -40 °C to +125 °C  
 
 

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