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74AUP1T45GM PDF预览

74AUP1T45GM

更新时间: 2024-01-24 15:13:17
品牌 Logo 应用领域
恩智浦 - NXP /
页数 文件大小 规格书
33页 167K
描述
Low-power dual supply translating transceiver; 3-state

74AUP1T45GM 数据手册

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74AUP1T45  
NXP Semiconductors  
Low-power dual supply translating transceiver; 3-state  
6. Pinning information  
6.1 Pinning  
74AUP1T45  
74AUP1T45  
V
1
2
3
6
5
4
V
CC(B)  
CC(A)  
GND  
74AUP1T45  
1
2
3
6
5
4
V
V
CC(B)  
V
1
2
3
6
5
4
V
CC(B)  
CC(A)  
GND  
CC(A)  
GND  
DIR  
B
DIR  
B
DIR  
B
A
A
A
001aae965  
001aae966  
Transparent top view  
Transparent top view  
001aae964  
Fig 3. Pin configuration SOT363  
(SC-88)  
Fig 4. Pin configuration SOT886  
(XSON6)  
Fig 5. Pin configuration SOT891  
(XSON6)  
6.2 Pin description  
Table 3.  
Symbol  
VCC(A)  
GND  
A
Pin description  
Pin  
Description  
1
2
3
4
5
6
supply voltage port A  
ground (0 V)  
data input or output A  
data input or output B  
direction control DIR  
supply voltage port B  
B
DIR  
VCC(B)  
7. Functional description  
Table 4.  
Function table[1]  
Supply voltage  
VCC(A), VCC(B)  
1.1 V to 3.6 V  
1.1 V to 3.6 V  
GND  
Input[2]  
Input/output[3]  
DIR  
L
A
B
A = B  
input  
H
input  
B = A  
X
suspend mode  
suspend mode  
[1] H = HIGH voltage level;  
L = LOW voltage level;  
X = don’t care.  
[2] The DIR input circuit is referenced to VCC(A)  
.
[3] The input circuit of the data I/Os are always active.  
74AUP1T45_1  
© NXP B.V. 2006. All rights reserved.  
Product data sheet  
Rev. 01 — 18 October 2006  
3 of 33  

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