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74AUP1T14GX PDF预览

74AUP1T14GX

更新时间: 2024-10-29 11:11:43
品牌 Logo 应用领域
安世 - NEXPERIA /
页数 文件大小 规格书
14页 229K
描述
Low-power inverter with voltage-level translatorProduction

74AUP1T14GX 数据手册

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Nexperia  
74AUP1T14  
Low-power inverter with voltage-level translator  
V
V
EXT  
CC  
5 kΩ  
V
I
V
O
G
DUT  
R
T
C
L
R
L
001aac521  
Test data is given in Table 10.  
Definitions for test circuit:  
RL = Load resistance;  
CL = Load capacitance including jig and probe capacitance;  
RT = Termination resistance should be equal to the output impedance Zo of the pulse generator;  
VEXT = External voltage for measuring switching times.  
Fig. 7. Test circuit for measuring switching times  
Table 10. Test data  
Supply voltage  
VCC  
Load  
VEXT  
CL  
RL [1]  
tPLH, tPHL  
open  
tPZH, tPHZ  
tPZL, tPLZ  
2.3 V to 3.6 V  
5 pF, 10 pF, 15 pF and 30 pF  
5 kΩ or 1 MΩ  
GND  
2 × VCC  
[1] For measuring enable and disable times RL = 5 kΩ.  
For measuring propagation delays, setup and hold times and pulse width RL = 1 MΩ.  
©
74AUP1T14  
All information provided in this document is subject to legal disclaimers.  
Nexperia B.V. 2022. All rights reserved  
Product data sheet  
Rev. 3 — 25 January 2022  
9 / 14  
 
 
 

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