74AUP1T45GM

更新时间： 2024-02-22 21:38:30

品牌	Logo	应用领域
恩智浦 - NXP		/
页数	文件大小	规格书
33页	167K
描述
Low-power dual supply translating transceiver; 3-state

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74AUP1T45GM 数据手册

74AUP1T45

Low-power dual supply translating transceiver; 3-state

Rev. 01 — 18 October 2006

Product data sheet

1. General description

The 74AUP1T45 is a high-performance, low-power, low-voltage, Si-gate CMOS device,

superior to most advanced CMOS compatible TTL families.

The 74AUP1T45 is a single bit transceiver featuring two data input-outputs (A and B), a

direction control input (DIR) and dual supply pins (V_CC(A)and V_CC(B)) which enable

bidirectional level translation. Both V_CC(A)and V_CC(B)can be supplied at any voltage

between 1.1 V and 3.6 V making the device suitable for interfacing between any of the low

voltage nodes (1.2 V, 1.5 V, 1.8 V, 2.5 V and 3.3 V). Pins A and DIR are referenced to

V_CC(A)and pin B is referenced to V_CC(B). A HIGH on DIR allows transmission from A to B

and a LOW on DIR allows transmission from B to A.

Schmitt trigger action on all inputs makes the circuit tolerant of slower input rise and fall

times across the entire V_CC(A)and V_CC(B)ranges. The device ensures low static and

dynamic power consumption and is fully speciﬁed for partial power-down applications

using I_OFF. The I_OFFcircuitry disables the output, preventing any damaging backﬂow

current through the device when it is powered down. In suspend mode when either V_CC(A)

or V_CC(B)are at GND, both A and B are in the high-impedance OFF-state.

2. Features

I Wide supply voltage range:

N V_CC(A): 1.1 V to 3.6 V

N V_CC(B): 1.1 V to 3.6 V

I High noise immunity

I Complies with JEDEC standards:

N JESD8-7 (1.2 V to 1.95 V)

N JESD8-5 (1.8 V to 2.7 V)

N JESD8-B (2.7 V to 3.6 V)

I ESD protection:

N HBM JESD22-A114-D Class 3A exceeds 5000 V

N MM JESD22-A115-A exceeds 200 V

N CDM JESD22-C101-C exceeds 1000 V

I Low static power consumption; I_CC= 0.9 µA (maximum)

I Suspend mode

I Latch-up performance exceeds 100 mA per JESD 78 Class II

I Inputs accept voltages up to 3.6 V

I Low noise overshoot and undershoot < 10 % of V_CC

I I_OFFcircuitry provides partial Power-down mode operation

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