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74ALVCH16500DLG4 PDF预览

74ALVCH16500DLG4

更新时间： 2024-09-16 15:32:07
品牌 Logo 应用领域
德州仪器 - TI 光电二极管输出元件逻辑集成电路
页数 文件大小 规格书
15页 339K
描述
ALVC/VCX/A SERIES, 18-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDSO56, 0.300 INCH, GREEN, PLASTIC, SSOP-56

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74ALVCH16500DLG4 技术参数

是否无铅： 含铅是否Rohs认证： 符合
生命周期：Obsolete零件包装代码：SSOP
包装说明：SSOP,针数：56
Reach Compliance Code：compliant风险等级：5.56
其他特性：WITH INDEPENDENT OUTPUT ENABLE FOR EACH DIRECTION系列：ALVC/VCX/A
JESD-30 代码：R-PDSO-G56JESD-609代码：e4
长度：18.415 mm逻辑集成电路类型：REGISTERED BUS TRANSCEIVER
湿度敏感等级：1位数：18
功能数量：1端口数量：2
端子数量：56最高工作温度：85 °C
最低工作温度：-40 °C输出特性：3-STATE
输出极性：TRUE封装主体材料：PLASTIC/EPOXY
封装代码：SSOP封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, SHRINK PITCH峰值回流温度（摄氏度）：260
传播延迟（tpd）：6.6 ns认证状态：Not Qualified
座面最大高度：2.79 mm最大供电电压 (Vsup)：3.6 V
最小供电电压 (Vsup)：1.65 V标称供电电压 (Vsup)：1.8 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式：GULL WING端子节距：0.635 mm
端子位置：DUAL处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：7.49 mmBase Number Matches：1

74ALVCH16500DLG4 数据手册

 浏览型号74ALVCH16500DLG4的Datasheet PDF文件第2页浏览型号74ALVCH16500DLG4的Datasheet PDF文件第3页浏览型号74ALVCH16500DLG4的Datasheet PDF文件第4页浏览型号74ALVCH16500DLG4的Datasheet PDF文件第5页浏览型号74ALVCH16500DLG4的Datasheet PDF文件第6页浏览型号74ALVCH16500DLG4的Datasheet PDF文件第7页 
SN74ALVCH16500  
18-BIT UNIVERSAL BUS TRANSCEIVER  
WITH 3-STATE OUTPUTS  
www.ti.com  
SCES023I–JULY 1995–REVISED OCTOBER 2004  
FEATURES  
DGG OR DL PACKAGE  
(TOP VIEW)  
•
•
•
Member of the Texas Instruments Widebus™  
Family  
1
OEAB  
LEAB  
A1  
56 GND  
EPIC™ (Enhanced-Performance Implanted  
CMOS) Submicron Process  
2
55 CLKAB  
3
54  
B1  
UBT™ (Universal Bus Transceiver) Combines  
D-Type Latches and D-Type Flip-Flops for  
Operation in Transparent, Latched, or Clocked  
Modes  
4
GND  
A2  
53 GND  
52 B2  
5
6
A3  
51 B3  
7
V
50  
49  
48  
47  
V
CC  
CC  
•
ESD Protection Exceeds 2000 V Per  
8
A4  
A5  
A6  
B4  
B5  
B6  
MIL-STD-883, Method 3015; Exceeds 200 V  
Using Machine Model (C = 200 pF, R = 0)  
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
•
•
•
Latch-UP Performance Exceeds 250 mA Per  
JESD 17  
GND  
A7  
A8  
46 GND  
45 B7  
Bus Hold on Data Inputs Eliminates the Need  
for External Pullup/Pulldown Resistors  
44 B8  
43  
42  
41  
40  
A9  
B9  
Package Options Include Plastic 300-mil  
Shrink Small-Outline (DL) and Thin Shrink  
Small-Outline (DGG) Packages  
A10  
A11  
A12  
GND  
A13  
A14  
A15  
B10  
B11  
B12  
39 GND  
DESCRIPTION  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
B13  
B14  
B15  
This 18-bit universal bus transceiver is designed for  
1.65-V to 3.6-V VCC operation.  
V
CC  
V
CC  
Data flow in each direction is controlled by  
output-enable (OEAB and OEBA), latch-enable  
(LEAB and LEBA), and clock (CLKAB and CLKBA)  
inputs. For A-to-B data flow, the device operates in  
the transparent mode when LEAB is high. When  
LEAB is low, the A data is latched if CLKAB is held at  
a high or low logic level. If LEAB is low, the A data is  
stored in the latch/flip-flop on the high-to-low  
transition of CLKAB. Output-enable OEAB is active  
high. When OEAB is high, the B-port outputs are  
active. When OEAB is low, the B-port outputs are in  
the high-impedance state.  
A16  
A17  
B16  
B17  
GND  
A18  
OEBA  
LEBA  
GND  
B18  
CLKBA  
GND  
xxxxxx  
Data flow for B to A is similar to that of A to B, but uses OEBA, LEBA, and CLKBA. The output enables are  
complementary (OEAB is active high, and OEBA is active low).  
To ensure the high-impedance state during power up or power down, OEBA should be tied to VCC through a  
pullup resistor, and OEAB should be tied to GND through a pulldown resistor; the minimum value of the resistor  
is determined by the current-sinking/current-sourcing capability of the driver.  
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.  
The SN74ALVCH16500 is characterized for operation from -40°C to 85°C.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Widebus, EPIC, UBT are trademarks of Texas Instruments.  
PRODUCTION DATA information is current as of publication date.  
Copyright © 1995–2004, Texas Instruments Incorporated  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
1234567...15

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74ALVCH16500DLG4 替代型号

型号 品牌 替代类型 描述 数据表
SN74ALVCH16500DLR TI

完全替代

 具有三态输出的 18 位通用总线收发器 | DL | 56 | -40 to 85

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