Datasheet > 74ALVCH16501DGG

74ALVCH16501DGG

更新时间： 2024-09-17 11:15:39

品牌	Logo	应用领域
安世 - NEXPERIA		光电二极管逻辑集成电路触发器
页数	文件大小	规格书
15页	249K
描述
18-bit universal bus transceiver; 3-stateProduction

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74ALVCH16501DGG 数据手册

74ALVCH16501

18-bit universal bus transceiver; 3-state

Rev. 7 — 24 November 2021

Product data sheet

1. General description

The 74ALVCH16501 is an 18-bit universal transceiver with bus hold inputs and 3-state outputs.

Data flow in each direction is controlled by output enable (OEAB and OEBA), latch enable (LEAB

and LEBA), and clock (CPAB and CPBA) inputs. For A-to-B data flow, the device operates in the

transparent mode when LEAB is HIGH. When LEAB is LOW, the A data is latched if CPAB is held

at a HIGH or LOW logic level. If LEAB is LOW, the A-bus data is stored in the latch/flip-flop on the

LOW-to-HIGH transition of CPAB. When OEAB is HIGH, the outputs are active. When OEAB is

LOW, the outputs are in the high-impedance state. Data flow for B-to-A is similar to that of A-to-B

but uses OEBA, LEBA and CPBA. The output enables are complimentary (OEAB is active HIGH

and OEBA is active LOW). This device is fully specified for partial power down applications using

I_OFF. The I_OFFcircuitry disables the output, preventing the potentially damaging backflow current

through the device when it is powered down.

2. Features and benefits

•

Wide supply voltage range from 1.2 V to 3.6 V

•

CMOS low power dissipation

Direct interface with TTL levels

Current drive ±24 mA at V_CC= 3.0 V

Universal bus transceiver with D-type latches and D-type flip-flops capable of operating in

transparent, latched or clocked mode

•

Bus hold on all data inputs

Output drive capability 50 Ω transmission lines at 85 °C

3-state non-inverting outputs for bus-oriented applications

Latch-up performance exceeds 100 mA per JESD78 Class II Level B

Complies with JEDEC standards:

•

JESD8-7 (1.65 V to 1.95 V)

JESD8-5 (2.3 V to 2.7 V)

JESD8C (2.7 V to 3.6 V)

•

ESD protection:

•

HBM JESD22-A114F exceeds 2000 V

MM JESD22-A115-B exceeds 200 V

Specified from -40 °C to +85 °C

3. Ordering information

Table 1. Ordering information

Type number

Package

Temperature range Name

Description

Version

74ALVCH16501DGG -40 °C to +85 °C

TSSOP56

plastic thin shrink small outline package;

56 leads; body width 6.1 mm

SOT364-1

12 3 4 5 6 7...15

中文翻译

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与74ALVCH16501DGG相关器件

型号	品牌	获取价格	描述	数据表
74ALVCH16501DGG,11	NXP	获取价格	74ALVCH16501 - 18-bit universal bus transceiver; 3-state TSSOP 56-Pin
74ALVCH16501DGG:11	NXP	获取价格	74ALVCH16501 - 18-bit universal bus transceiver; 3-state TSSOP 56-Pin
74ALVCH16501DGGRG4	TI	获取价格	18-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS
74ALVCH16501DGGS	NXP	获取价格	74ALVCH16501 - 18-bit universal bus transceiver; 3-state TSSOP 56-Pin
74ALVCH16501DGG-T	ETC	获取价格	18-Bit Bus Transceiver
74ALVCH16501DGGY	NXP	获取价格	74ALVCH16501 - 18-bit universal bus transceiver; 3-state TSSOP 56-Pin
74ALVCH16501DL	NXP	获取价格	18-bit universal bus transceiver; 3-state
74ALVCH16501DL,112	NXP	获取价格	74ALVCH16501 - 18-bit universal bus transceiver; 3-state SSOP 56-Pin
74ALVCH16501DL,118	NXP	获取价格	74ALVCH16501 - 18-bit universal bus transceiver; 3-state SSOP 56-Pin
74ALVCH16501DLG4	TI	获取价格	18-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS

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