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74ALVCH162374PA PDF预览

74ALVCH162374PA

更新时间: 2024-11-18 21:22:03
品牌 Logo 应用领域
艾迪悌 - IDT 驱动光电二极管逻辑集成电路触发器
页数 文件大小 规格书
6页 246K
描述
Bus Driver, ALVC/VCX/A Series, 2-Func, 8-Bit, True Output, CMOS, PDSO48, TSSOP-48

74ALVCH162374PA 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:TSSOP包装说明:TSSOP, TSSOP48,.3,20
针数:48Reach Compliance Code:not_compliant
风险等级:5.76系列:ALVC/VCX/A
JESD-30 代码:R-PDSO-G48JESD-609代码:e0
长度:12.5 mm负载电容(CL):50 pF
逻辑集成电路类型:BUS DRIVER最大I(ol):0.012 A
湿度敏感等级:1位数:8
功能数量:2端口数量:2
端子数量:48最高工作温度:85 °C
最低工作温度:-40 °C输出特性:3-STATE
输出极性:TRUE封装主体材料:PLASTIC/EPOXY
封装代码:TSSOP封装等效代码:TSSOP48,.3,20
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
电源:3.3 V传播延迟(tpd):5.4 ns
认证状态:Not Qualified座面最大高度:1.2 mm
子类别:FF/Latches最大供电电压 (Vsup):3.6 V
最小供电电压 (Vsup):2.7 V标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:Tin/Lead (Sn85Pb15)
端子形式:GULL WING端子节距:0.5 mm
端子位置:DUAL触发器类型:POSITIVE EDGE
宽度:6.1 mmBase Number Matches:1

74ALVCH162374PA 数据手册

 浏览型号74ALVCH162374PA的Datasheet PDF文件第2页浏览型号74ALVCH162374PA的Datasheet PDF文件第3页浏览型号74ALVCH162374PA的Datasheet PDF文件第4页浏览型号74ALVCH162374PA的Datasheet PDF文件第5页浏览型号74ALVCH162374PA的Datasheet PDF文件第6页 
3.3V CMOS 16-BIT EDGE-  
IDT74ALVCH162374  
TRIGGERED D-TYPE FLIP-  
FLOP WITH 3-STATE OUTPUTS  
AND BUS-HOLD  
FEATURES:  
DESCRIPTION:  
• 0.5 MICRON CMOS Technology  
Typical tSK(o) (Output Skew) < 250ps  
• ESD > 2000V per MIL-STD-883, Method 3015; > 200V using  
machine model (C = 200pF, R = 0)  
This16-bitedge-triggeredD-typeflip-flopisbuiltusingadvanceddualmetal  
CMOStechnology.TheALVCH162374isparticularlysuitableforimplementing  
bufferregisters,I/Oports,bidirectionalbusdrivers,andworkingregisters.Itcan  
beusedastwo8-bitflip-flopsorone16-bitflip-flop.Onthepositivetransitionof  
theclock(CLK)input,theQoutputsoftheflip-floptakeonthelogiclevelssetup  
atthedata(D)inputs.OEcanbeusedtoplacetheeightoutputsineitheranormal  
logic state (high or low logic levels) or a high-impedance state. In the high-  
impedancestate,theoutputsneitherloadnordrivethebuslinessignificantly.  
The high-impedance state and the increased drive provide the capability to  
drivebuslineswithoutneedforinterfaceorpullupcomponents.OEdoesnot  
affectinternaloperationsoftheflip-flop.Olddatacanberetainedornewdata  
canbeenteredwhiletheoutputsareinthehigh-impedancestate.  
VCC = 3.3V ± 0.3V, Normal Range  
VCC = 2.7V to 3.6V, Extended Range  
VCC = 2.5V ± 0.2V  
• CMOS power levels (0.4μ W typ. static)  
• Rail-to-Rail output swing for increased noise margin  
Available in TSSOP package  
DRIVE FEATURES:  
• Balanced Output Drivers: ±12mA  
Low switching noise  
TheALVCH162374hasseriesresistorsinthedeviceoutputstructurewhich  
willsignificantlyreducelinenoisewhenusedwithlightloads.Thisdriverhas  
beendesignedtodrive±12mAatthedesignatedthresholdlevels.  
The ALVCH162374 has bus-hold” which retains the inputs’ last state  
whenevertheinputgoestoahighimpedance.Thispreventsfloatinginputsand  
eliminatestheneedforpull-up/downresistor.  
APPLICATIONS:  
• 3.3V high speed systems  
• 3.3V and lower voltage computing systems  
FUNCTIONALBLOCKDIAGRAM  
1
24  
2OE  
1OE  
48  
25  
2CLK  
1CLK  
C1  
C1  
2
13  
1Q1  
2Q1  
47  
36  
1D1  
1D  
1D  
2D1  
TO 7 OTHER CHANNELS  
TO 7 OTHER CHANNELS  
TheIDTlogoisaregisteredtrademarkofIntegratedDeviceTechnology,Inc.  
INDUSTRIAL TEMPERATURE RANGE  
February 19, 2009  
1
© 1999 Integrated Device Technology, Inc.  
DSC-4565/4  

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