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74ALVCH16244/D PDF预览

74ALVCH16244/D

更新时间: 2024-09-14 23:24:07
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描述
Low-Voltage 16-Bit Buffer with Bus Hold 1.8/2.5/3.3 V

74ALVCH16244/D 数据手册

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74ALVCH16244  
Low-Voltage 16-Bit Buffer  
with Bus Hold 1.8/2.5/3.3 V  
(3–State, Non–Inverting)  
The 74ALVCH16244 is an advanced performance, non–inverting  
16–bit buffer. It is designed for very high–speed, very low–power  
operation in 1.8 V, 2.5 V or 3.3 V systems.  
http://onsemi.com  
The 74ALVCH16244 is nibble controlled with each nibble  
functioning identically, but independently. The control pins may be  
tied together to obtain full 16–bit operation. The 3–state outputs are  
controlled by an Output Enable (OEn) input for each nibble. When  
OEn is LOW, the outputs are on. When OEn is HIGH, the outputs are  
in the high impedance state. The data inputs include active bushold  
circuitry, eliminating the need for external pull–up resistors to hold  
unused or floating inputs at a valid logic state.  
MARKING DIAGRAM  
48  
48  
74ALVCH16244DT  
AWLYYWW  
1
TSSOP–48  
DT SUFFIX  
CASE 1201  
Designed for Low Voltage Operation: V = 1.65 – 3.6 V  
CC  
1
= Assembly Location  
3.6 V Tolerant Inputs and Outputs  
High Speed Operation: 3.0 ns max for 3.0 to 3.6 V  
3.7 ns max for 2.3 to 2.7 V  
A
WL = Wafer Lot  
6.0 ns max for 1.65 to 1.95 V  
YY = Year  
WW = Work Week  
Static Drive:  
±24 mA Drive at 3.0 V  
±12 mA Drive at 2.3 V  
±4 mA Drive at 1.65 V  
Supports Live Insertion and Withdrawal  
ORDERING INFORMATION  
Includes Active Bushold to Hold Unused or Floating Inputs at a Valid  
Logic State  
Device  
Package  
Shipping  
I  
Specification Guarantees High Impedance When V = 0 V  
CC  
OFF  
74ALVCH16244DTR TSSOP 2500/Tape & Reel  
Near Zero Static Supply Current in All Three Logic States (40 mA)  
Substantially Reduces System Power Requirements  
Latchup Performance Exceeds ±250 mA @ 125°C  
ESD Performance: Human Body Model >2000V; Machine Model >200V  
Second Source to Industry Standard 74ALVCH16244  
To ensure the outputs activate in the 3–state condition, the output enable pins  
should be connected to V through a pull–up resistor. The value of the resistor is  
CC  
determined by the current sinking capability of the output connected to the OE pin.  
Semiconductor Components Industries, LLC, 2002  
1
Publication Order Number:  
September, 2002 – Rev. 1  
74ALVCH16244/D  

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