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74ALVCH16244BFG PDF预览

74ALVCH16244BFG

更新时间: 2024-11-06 01:08:11
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页数 文件大小 规格书
7页 106K
描述
3.3V CMOS 32-BIT BUFFER/ DRIVER

74ALVCH16244BFG 数据手册

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3.3V CMOS 32-BIT  
IDT74ALVCH32244  
BUFFER/ DRIVER WITH  
3-STATE OUTPUTS AND  
BUS-HOLD  
DESCRIPTION:  
FEATURES:  
This 32-bit buffer/driver is built using advanced dual metal CMOS  
technology. This high-speed, low power device offers bus/backplane  
interface capabilitywithimprovedpackingdensity.The device has a flow-  
throughorganizationforsimplifyingboardlayout.Thethree-statecontrols  
operatethisdeviceinaQuad-Nibble,Dual-Byteorsingle16-bitwordmode.  
Allinputs are designedwithhysteresis forimprovednoise margin.  
The ALVCH32244has beendesignedwitha ±24mAoutputdriver.This  
driver is capable of driving a moderate to heavy load while maintaining  
speedperformance.  
• 0.5 MICRON CMOS Technology  
Typical tSK(o) (Output Skew) < 250ps  
• ESD > 2000V per MIL-STD-883, Method 3015; > 200V using  
machine model (C = 200pF, R = 0)  
VCC = 3.3V ± 0.3V, Normal Range  
VCC = 2.7V to 3.6V, Extended Range  
VCC = 2.5V ± 0.2V  
• CMOS power levels (0.4μ W typ. static)  
• Rail-to-Rail output swing for increased noise margin  
Available in 96-ball LFBGA package  
The ALVCH32244 has bus-hold” which retains the inputs’ last state  
wheneverthe inputbus goes toa highimpedance. This prevents floating  
inputs andeliminates the needforpull-up/downresistors.  
DRIVE FEATURES:  
High Output Drivers: ±24mA  
• Suitable for Heavy Loads  
APPLICATIONS:  
• 3.3V high speed systems  
• 3.3V and lower voltage computing systems  
FUNCTIONALBLOCKDIAGRAM  
J3  
J5  
A3  
A5  
H4  
E5  
T4  
N5  
3
OE  
7
OE  
1
OE  
5
OE  
A2  
E2  
J2  
N2  
1
Y1  
3Y1  
5
Y1  
7Y  
1
1A1  
5A1  
3A1  
7A1  
A1  
B2  
A6  
B5  
B6  
J1  
N6  
P5  
N1  
P2  
P1  
E6  
F5  
F6  
E1  
F2  
J6  
1
Y
2
5
Y
2
1
A
A
A
2
5
A
A
A
2
3
Y
2
3
7
Y
2
3
3
A
2
7
A
2
K2  
K1  
K5  
K6  
1
Y
3
5
Y
3
3
Y
7
Y
1
1
3
4
5
5
3
4
3
A
3
4
7
A
3
4
B1  
F1  
P6  
1Y4  
5Y4  
3A  
3Y  
4
7Y  
4
7A  
A4  
J4  
L5  
T3  
H3  
2
OE  
6
OE  
4
OE  
8
OE  
C5  
C6  
D5  
D6  
L2  
C2  
C1  
D2  
D1  
G2  
G1  
H1  
H2  
R5  
R6  
T6  
T5  
R2  
R1  
T1  
T2  
G5  
G6  
H6  
H5  
2
Y
1
6
Y
1
4Y1  
8Y1  
2A1  
6A1  
4A1  
8A1  
L6  
L1  
2Y  
2
3
6Y  
2
3
4
Y
2
3
8
Y
2
3
2
A2  
6
A2  
4
A2  
8
A2  
M2  
M5  
M6  
2
Y
6
Y
4
Y
8
Y
2
A
3
4
6
A
3
4
4
A
3
4
8
A
3
4
M1  
2
A
2Y  
4
6Y  
4
6
A
4
A
4Y4  
8Y  
4
8
A
IDTandtheIDTlogoareregisteredtrademarksofIntegratedDeviceTechnology,Inc.  
INDUSTRIAL TEMPERATURE RANGE  
AUGUST 2015  
1
©2015 Integrated Device Technology, Inc.  
DSC-4906/6  

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