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74ALVCH16244MTD PDF预览

74ALVCH16244MTD

更新时间: 2024-11-05 13:04:55
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 驱动器
页数 文件大小 规格书
6页 82K
描述
Bus Driver, ALVC/VCX/A Series, 4-Func, 4-Bit, True Output, CMOS, PDSO48, 6.10 MM, MO-153, TSSOP-48

74ALVCH16244MTD 技术参数

生命周期:Obsolete零件包装代码:TSSOP
包装说明:6.10 MM, MO-153, TSSOP-48针数:48
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.05Is Samacsys:N
系列:ALVC/VCX/AJESD-30 代码:R-PDSO-G48
长度:12.5 mm逻辑集成电路类型:BUS DRIVER
位数:4功能数量:4
端口数量:2端子数量:48
最高工作温度:85 °C最低工作温度:-40 °C
输出特性:3-STATE输出极性:TRUE
封装主体材料:PLASTIC/EPOXY封装代码:TSSOP
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
传播延迟(tpd):6 ns认证状态:Not Qualified
座面最大高度:1.2 mm最大供电电压 (Vsup):3.6 V
最小供电电压 (Vsup):1.65 V标称供电电压 (Vsup):1.8 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子形式:GULL WING
端子节距:0.5 mm端子位置:DUAL
宽度:6.1 mmBase Number Matches:1

74ALVCH16244MTD 数据手册

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September 2001  
Revised February 2002  
74ALVCH16244  
Low Voltage 16-Bit Buffer/Line Driver with Bushold  
General Description  
Features  
The ALVCH16244 contains sixteen non-inverting buffers  
with 3-STATE outputs to be employed as a memory and  
address driver, clock driver, or bus oriented transmitter/  
receiver. The device is nibble (4-bit) controlled. Each nibble  
has separate 3-STATE control inputs which can be shorted  
together for full 16-bit operation.  
1.65V to 3.6V VCC supply operation  
3.6V tolerant control inputs and outputs  
Bushold on data inputs eliminating the need for external  
pull-up/pull-down resistors  
tPD  
The ALVCH16244 data inputs include active bushold cir-  
cuitry, eliminating the need for external pull-up resistors to  
hold unused or floating data inputs at a valid logic level.  
3 ns max for 3.0V to 3.6V VCC  
3.7 ns max for 2.3V to 2.7V VCC  
6.0 ns max for 1.65V to 1.95V VCC  
The 74ALVCH16244 is designed for low voltage (1.65V to  
3.6V) VCC applications with output capability up to 3.6V.  
Uses patented noise/EMI reduction circuitry  
Latch-up conforms to JEDEC JED78  
ESD performance:  
The 74ALVCH16244 is fabricated with an advanced CMOS  
technology to achieve high speed operation while maintain-  
ing low CMOS power dissipation.  
Human body model > 2000V  
Machine model > 200V  
Ordering Code:  
Package  
Order Number  
Package Description  
Number  
74ALVCH16244T  
MTD48  
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide  
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.  
Logic Symbol  
Pin Descriptions  
Pin Names  
Description  
OEn  
Output Enable Input (Active LOW)  
Bushold Inputs  
I0I15  
O0O15  
Outputs  
© 2002 Fairchild Semiconductor Corporation  
DS500625  
www.fairchildsemi.com  

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