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74ALVCH16240PA PDF预览

74ALVCH16240PA

更新时间: 2024-11-05 20:09:47
品牌 Logo 应用领域
艾迪悌 - IDT 驱动光电二极管逻辑集成电路
页数 文件大小 规格书
6页 83K
描述
TSSOP-48, Tube

74ALVCH16240PA 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Obsolete零件包装代码:TSSOP
包装说明:TSSOP, TSSOP48,.3,20针数:48
Reach Compliance Code:not_compliant风险等级:5.81
控制类型:ENABLE LOWJESD-30 代码:R-PDSO-G48
JESD-609代码:e0逻辑集成电路类型:BUS DRIVER
最大I(ol):0.024 A湿度敏感等级:1
位数:4功能数量:4
端子数量:48最高工作温度:85 °C
最低工作温度:-40 °C输出特性:3-STATE
输出极性:INVERTED封装主体材料:PLASTIC/EPOXY
封装代码:TSSOP封装等效代码:TSSOP48,.3,20
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
电源:3.3 VProp。Delay @ Nom-Sup:3.9 ns
认证状态:Not Qualified子类别:Bus Driver/Transceivers
标称供电电压 (Vsup):3.3 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:Tin/Lead (Sn85Pb15)端子形式:GULL WING
端子节距:0.5 mm端子位置:DUAL
Base Number Matches:1

74ALVCH16240PA 数据手册

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3.3V CMOS 16-BIT  
IDT74ALVCH16240  
BUFFER/DRIVER WITH  
3-STATE OUTPUTS AND  
BUS-HOLD  
DESCRIPTION:  
FEATURES:  
0.5 MICRON CMOS Technology  
TypicaltSK(0) (Output Skew) < 250ps  
This 16-bit buffer/driver is built using advanced dual metal CMOS  
technology. The ALVCH16240 is deigned specifically to improve the  
performance and density of 3-state memory address drivers, clock  
drivers, and bus-oriented receivers and transmitters. The device can be  
used as four 4-bit buffers, two 8-bit buffers, or one 16-bit buffer. It  
provides inverting outputs and symmetrical active-low output-enable  
(OE) inputs.  
ESD > 2000V per MIL-STD-883, Method 3015;  
> 200V using machine model (C = 200pF, R = 0)  
0.635mm pitch SSOP, 0.50mm pitch TSSOP,  
and 0.40mm pitch TVSOP packages  
Extended commercial range of – 40°C to + 85°C  
VCC = 3.3V ± 0.3V, Normal Range  
VCC = 2.7V to 3.6V, Extended Range  
VCC = 2.5V ± 0.2V  
CMOS power levels (0.4µW typ. static)  
Rail-to-Rail output swing for increased noise margin  
The ALVCH16240 has been designed with a ±24mA output driver.  
This driver is capable of driving a moderate to heavy load while  
maintaining speed performance.  
Drive Features for ALVCH16240:  
The ALVCH16240 has bus-hold” which retains the inputs’ last state  
whenever the input bus goes to a high impedance. This prevents floating  
inputs and eliminates the need for pull-up/down resistors.  
High Output Drivers: ±24mA  
Suitable for heavy loads  
APPLICATIONS:  
3.3V High Speed Systems  
3.3V and lower voltage computing systems  
Functional Block Diagram  
25  
1
1OE  
3OE  
36  
13  
47  
2
1Y1  
1Y2  
1Y3  
1Y4  
3Y1  
3Y2  
3Y3  
3Y4  
1A1  
3A1  
3
5
35  
33  
14  
16  
17  
46  
44  
1A2  
3A2  
1A3  
3A3  
32  
43  
6
1A4  
3A4  
24  
48  
2OE  
2A1  
4OE  
8
30  
29  
27  
26  
19  
41  
40  
38  
37  
2Y1  
4Y1  
4A1  
4A2  
4A3  
9
11  
12  
20  
22  
23  
2A2  
2Y2  
2Y3  
2Y4  
4Y2  
4Y3  
4Y4  
2A3  
2A4  
4A4  
EXTENDED COMMERCIAL TEMPERATURE RANGE  
MARCH1999  
1
c
1999 Integrated Device Technology, Inc.  
DSC-4485/1  

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